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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/114668] [14] RISC-V rv64gcv: miscompile at -O3 Date: Mon, 15 Apr 2024 13:12:27 +0000 [thread overview] Message-ID: <bug-114668-4-KfLT5Pyycv@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-114668-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114668 --- Comment #3 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Robin Dapp <rdapp@gcc.gnu.org>: https://gcc.gnu.org/g:02cc8f3e68f9af96d484d9946ceaa9e3eed38151 commit r14-9972-g02cc8f3e68f9af96d484d9946ceaa9e3eed38151 Author: Robin Dapp <rdapp@ventanamicro.com> Date: Mon Apr 15 12:44:56 2024 +0200 RISC-V: Add VLS to mask vec_extract [PR114668]. This adds the missing VLS modes to the mask extract expanders. gcc/ChangeLog: PR target/114668 * config/riscv/autovec.md: Add VLS. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr114668.c: New test.
next prev parent reply other threads:[~2024-04-15 13:12 UTC|newest] Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-04-09 21:55 [Bug target/114668] New: " patrick at rivosinc dot com 2024-04-09 22:00 ` [Bug target/114668] " pinskia at gcc dot gnu.org 2024-04-10 15:35 ` rdapp at gcc dot gnu.org 2024-04-15 13:12 ` cvs-commit at gcc dot gnu.org [this message] 2024-04-15 13:17 ` rdapp at gcc dot gnu.org
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