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From: "rdapp at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/114734] [14] RISC-V rv64gcv_zvl256b miscompile with -flto -O3 -mrvv-vector-bits=zvl Date: Tue, 16 Apr 2024 12:58:07 +0000 [thread overview] Message-ID: <bug-114734-4-5Xpt9lmZst@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-114734-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114734 --- Comment #3 from Robin Dapp <rdapp at gcc dot gnu.org> --- > probably -fwhole-program is enough, -flto not needed(?) Yes, -fwhole-program is sufficient. > > # vectp_g.248_1401 = PHI <vectp_g.248_1402(32), &g(143)> > ... > _1411 = .SELECT_VL (ivtmp_1409, POLY_INT_CST [2, 2]); > .. > vect__193.250_1403 = .MASK_LEN_LOAD (vectp_g.248_1401, 32B, { -1, ... }, > _1411, 0); > vect__194.251_1404 = -vect__193.250_1403; > vect_iftmp.252_1405 = (vector([2,2]) long int) vect__194.251_1404; > > # vect_iftmp.252_1406 = PHI <vect_iftmp.252_1405(5)> > # loop_len_1427 = PHI <_1411(5)> > ... > _1407 = loop_len_1427 + 18446744073709551615; > _1408 = .VEC_EXTRACT (vect_iftmp.252_1406, _1407); > iftmp.3_1204 = _1408; > > is stored to b[15]. Doesn't look too odd to me. At the assembly equivalent of > vect__193.250_1403 = .MASK_LEN_LOAD (vectp_g.248_1401, 32B, { -1, ... }, > _1411, 0); we load [3 3] (=f) instead of [0 0] (=g). f is located after g in memory and register a3 is increased before the loop latch. We then re-use a3 to load the last two elements of g but actually read the first two of f.
next prev parent reply other threads:[~2024-04-16 12:58 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-04-16 5:14 [Bug target/114734] New: " patrick at rivosinc dot com 2024-04-16 7:47 ` [Bug target/114734] " rdapp at gcc dot gnu.org 2024-04-16 7:51 ` rguenth at gcc dot gnu.org 2024-04-16 11:50 ` rguenth at gcc dot gnu.org 2024-04-16 12:58 ` rdapp at gcc dot gnu.org [this message] 2024-04-16 13:14 ` rdapp at gcc dot gnu.org 2024-04-22 15:45 ` rdapp at gcc dot gnu.org 2024-04-24 14:16 ` rdapp at gcc dot gnu.org 2024-04-25 6:31 ` rguenth at gcc dot gnu.org 2024-04-25 8:15 ` rdapp at gcc dot gnu.org 2024-04-25 13:28 ` rguenth at gcc dot gnu.org 2024-04-25 13:52 ` rdapp at gcc dot gnu.org 2024-04-26 13:45 ` [Bug target/114734] RISC-V rv64gcv_zvl256b miscompile with -flto -O3 -mrvv-vector-bits=zvl since r8-6047-g65dd1346027bb5 rguenth at gcc dot gnu.org 2024-04-26 13:52 ` rguenth at gcc dot gnu.org 2024-04-30 6:46 ` [Bug target/114734] [11/12/13/14/15 regression] " cvs-commit at gcc dot gnu.org 2024-04-30 6:47 ` [Bug target/114734] [11/12/13/14 " rguenth at gcc dot gnu.org 2024-04-30 14:50 ` patrick at rivosinc dot com 2024-05-02 16:22 ` cvs-commit at gcc dot gnu.org 2024-05-03 12:51 ` cvs-commit at gcc dot gnu.org 2024-05-03 12:51 ` cvs-commit at gcc dot gnu.org 2024-05-03 12:52 ` [Bug target/114734] [11/12/13 " rguenth at gcc dot gnu.org 2024-05-06 13:15 ` cvs-commit at gcc dot gnu.org 2024-05-06 13:15 ` cvs-commit at gcc dot gnu.org 2024-05-16 9:56 ` [Bug target/114734] [11/12 " cvs-commit at gcc dot gnu.org
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