[Bug target/114734] New: [14] RISC-V rv64gcv_zvl256b miscompile with -flto -O3 -mrvv-vector-bits=zvl

["patrick at rivosinc dot com" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114734

            Bug ID: 114734
           Summary: [14] RISC-V rv64gcv_zvl256b miscompile with -flto -O3
                    -mrvv-vector-bits=zvl
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: patrick at rivosinc dot com
  Target Milestone: ---

Testcase: 
int f[18];
int g[18];
int h[18][18][18];
int a[324];
long b[18];
int *i = g;
int (*j)[18][18] = h;
int z;
int main() {
  for (int m = 0; m < 18; ++m)
    f[m] = 3;
  for (int m = 0; m < 18; m += 1)
    for (int n = 0; n < 18; n += 3) {
      a[m * 8 + n] = j[m][m][0] ? i[n] : 0;
      b[n] = f[n] ? -i[m] : 0;
    }
  for (long n = 0; n < 8; ++n)
    z = a[n];
  __builtin_printf("%ld\n", b[15]);
}

Commands:
> /scratch/tc-testing/tc-apr-15/build-rv64gcv/bin/riscv64-unknown-linux-gnu-gcc -march=rv64gcv_zvl256b -flto -O3 -mrvv-vector-bits=zvl red.c -o red.out
> /scratch/tc-testing/tc-apr-15/build-rv64gcv/bin/qemu-riscv64 red.out
-3
> /scratch/tc-testing/tc-apr-15/build-rv64gcv/bin/riscv64-unknown-linux-gnu-gcc red.c -o red.out
> /scratch/tc-testing/tc-apr-15/build-rv64gcv/bin/qemu-riscv64 red.out
0

Result is not affected by -fno-strict-aliasing.

Tested using r14-9976-gf8409c3109d (not bisected)

Found via fuzzer.