[Bug rtl-optimization/114810] [14 Regression] internal compiler error: in lra_split_hard_reg_for, at lra-assigns.cc:1868 (unable to find a register to spill) {*andndi3_doubleword_bmi} with -m32 -mstackrealign -O2 -mbmi -fno-exceptions -fno-plt

["ubizjak at gmail dot com" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114810

--- Comment #7 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Vladimir Makarov from comment #6)
> The problem is that the alternative assumes 3 DI values live simultaneously.
> This means 6 regs and we have only 6 available ones. One input reg is
> assigned to 0 another one is to 3.  So we have [01]2[34]5, where regs in
> brackets are taken by the operands.  Although there are still 2 regs but
> they can not be used as they are not adjacent.
> 
> The one solution is to somehow penalize the chosen alternative by changing
> alternative heuristics in lra-constraints.cc.  But it definitely can affect
> other targets in some unpredicted way.  So the solution is too risky
> especially at this stage.  Also it might be possible that there is no
> alternative with less 3 living pseudos for some different insn case.
> 
> I don't see non-risky solution right now.  I'll be thinking how to better
> fix this.

Please note that the insn is defined as:

(define_insn_and_split "*andn<dwi>3_doubleword_bmi"
  [(set (match_operand:<DWI> 0 "register_operand" "=&r,r,r")
        (and:<DWI>
          (not:<DWI> (match_operand:<DWI> 1 "register_operand" "r,0,r"))
          (match_operand:<DWI> 2 "nonimmediate_operand" "ro,ro,0")))
   (clobber (reg:CC FLAGS_REG))]

where the problematic alternative (=&r,r,ro) allows a memory input in its
operand 2 constraint. The allocator could spill a DImode value to a stack in
advance and reload the value from the memory in this particular alternative.