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From: "vmakarov at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug rtl-optimization/114810] [14 Regression] internal compiler error: in lra_split_hard_reg_for, at lra-assigns.cc:1868  (unable to find a register to spill) {*andndi3_doubleword_bmi} with -m32 -mstackrealign -O2 -mbmi -fno-exceptions -fno-plt
Date: Mon, 22 Apr 2024 19:45:37 +0000	[thread overview]
Message-ID: <bug-114810-4-zGO4tl7eO0@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-114810-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114810

--- Comment #6 from Vladimir Makarov <vmakarov at gcc dot gnu.org> ---
(In reply to Uroš Bizjak from comment #4)
> An interesting observation, when the insn is defined only with problematic
> alternative:
> 
> (define_insn_and_split "*andn<dwi>3_doubleword_bmi"
>   [(set (match_operand:<DWI> 0 "register_operand" "=&r")
> 	(and:<DWI>
> 	  (not:<DWI> (match_operand:<DWI> 1 "register_operand" "r"))
> 	  (match_operand:<DWI> 2 "nonimmediate_operand" "ro")))
>    (clobber (reg:CC FLAGS_REG))]
> 
> the compilation succeeds, and a spill to memory is emitted:
> 
> 
> (insn 1170 65 1177 7 (set (mem/c:DI (plus:SI (reg/f:SI 6 bp)
>                 (const_int -168 [0xffffffffffffff58])) [71 %sfp+-144 S8 A64])
>         (reg:DI 0 ax [orig:217 _13 ] [217])) "pr114810.C":296:36 84
> {*movdi_internal}
>      (nil))
> 
> ...
> 
> (insn 987 1154 1111 7 (parallel [
>             (set (reg:DI 3 bx [453])
>                 (and:DI (not:DI (reg:DI 0 ax [452]))
>                     (mem/c:DI (plus:SI (reg/f:SI 6 bp)
>                             (const_int -168 [0xffffffffffffff58])) [71
> %sfp+-144 S8 A64])))
>             (clobber (reg:CC 17 flags))
>         ]) "pr114810.C":296:6 703 {*andndi3_doubleword_bmi}
>      (nil))

The problem is that the alternative assumes 3 DI values live simultaneously. 
This means 6 regs and we have only 6 available ones. One input reg is assigned
to 0 another one is to 3.  So we have [01]2[34]5, where regs in brackets are
taken by the operands.  Although there are still 2 regs but they can not be
used as they are not adjacent.

The one solution is to somehow penalize the chosen alternative by changing
alternative heuristics in lra-constraints.cc.  But it definitely can affect
other targets in some unpredicted way.  So the solution is too risky especially
at this stage.  Also it might be possible that there is no alternative with
less 3 living pseudos for some different insn case.

I don't see non-risky solution right now.  I'll be thinking how to better fix
this.

  parent reply	other threads:[~2024-04-22 19:45 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-04-22 17:57 [Bug target/114810] New: " kocelfc at tutanota dot com
2024-04-22 17:58 ` [Bug target/114810] " kocelfc at tutanota dot com
2024-04-22 18:22 ` jakub at gcc dot gnu.org
2024-04-22 19:10 ` ubizjak at gmail dot com
2024-04-22 19:23 ` ubizjak at gmail dot com
2024-04-22 19:31 ` [Bug rtl-optimization/114810] " ubizjak at gmail dot com
2024-04-22 19:45 ` vmakarov at gcc dot gnu.org [this message]
2024-04-22 20:07 ` ubizjak at gmail dot com
2024-04-22 21:36 ` jakub at gcc dot gnu.org
2024-04-22 21:48 ` vmakarov at gcc dot gnu.org
2024-04-22 21:56 ` jakub at gcc dot gnu.org
2024-04-23  5:53 ` ubizjak at gmail dot com
2024-04-23  6:02 ` ubizjak at gmail dot com
2024-04-23 12:29 ` jakub at gcc dot gnu.org
2024-04-23 12:46 ` ubizjak at gmail dot com
2024-04-23 21:31 ` cvs-commit at gcc dot gnu.org
2024-04-23 21:31 ` jakub at gcc dot gnu.org
2024-05-08 16:39 ` cvs-commit at gcc dot gnu.org

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