[Bug target/35363] Missing bit field coalescing optimization

[Bug target/35363] Missing bit field coalescing optimization

[xinliangli at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=35363

davidxl <xinliangli at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |xinliangli at gmail dot com
            Version|4.3.0                       |4.6.0

--- Comment #7 from davidxl <xinliangli at gmail dot com> 2010-11-03 00:20:46 UTC ---
(In reply to comment #6)
> The IL after MEM_REF lowering looks like
> 
> bar ()
> {
>   int D.1193;
>   unsigned int D.1192;
>   unsigned int D.1191;
>   unsigned int D.1190;
>   int D.1189;
> 
>   D.1189 = MEM <int {0}, &a>;
>   D.1190 = (unsigned int) D.1189;
>   D.1191 = D.1190 & 192;
>   D.1192 = D.1191 | 1048602;
>   D.1193 = (int) D.1192;
>   MEM <int {0}, &a> = D.1193;
>   return;
> }
> 
> foo ()
> {
>   int MEML.2;
>   int MEML.1;
>   int MEML.0;
> 
>   MEML.0 = MEM <int {0}, &a>;
>   MEML.0 = BIT_FIELD_EXPR <MEML.0, 2, 3, 0>;
>   MEM <int {0}, &a> = MEML.0;
>   MEML.1 = MEM <int {0}, &a>;
>   MEML.1 = BIT_FIELD_EXPR <MEML.1, 3, 3, 3>;
>   MEM <int {0}, &a> = MEML.1;
>   MEML.2 = MEM <int {0}, &a>;
>   MEML.2 = BIT_FIELD_EXPR <MEML.2, 8, 17, 8>;
>   MEM <int {0}, &a> = MEML.2;
>   return;
> }


LLVM generates expected code:

.Ltmp1:
    movl    $-33554240, %eax
    andl    a(%rip), %eax
    orl    $2074, %eax
    movl    %eax, a(%rip)

open64 is also bad.

[Bug target/35363] Missing bit field coalescing optimization

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=35363

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
             Status|NEW                         |RESOLVED
                 CC|                            |pinskia at gcc dot gnu.org
   Target Milestone|---                         |8.0

--- Comment #9 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Store merging fixes this for GCC 8 so closing as fixed:
  _5 = MEM[(struct A *)&a];
  _6 = _5 & 4261413056;
  _7 = _6 | 2074;
  MEM[(struct A *)&a] = _7;

I Will have to make sure we don't regress when adding lowering.

[Bug target/35363] Missing bit field coalescing optimization

[rguenth at gcc dot gnu dot org]

------- Comment #6 from rguenth at gcc dot gnu dot org  2008-02-25 18:54 -------
The IL after MEM_REF lowering looks like

bar ()
{
  int D.1193;
  unsigned int D.1192;
  unsigned int D.1191;
  unsigned int D.1190;
  int D.1189;

  D.1189 = MEM <int {0}, &a>;
  D.1190 = (unsigned int) D.1189;
  D.1191 = D.1190 & 192;
  D.1192 = D.1191 | 1048602;
  D.1193 = (int) D.1192;
  MEM <int {0}, &a> = D.1193;
  return;
}

foo ()
{
  int MEML.2;
  int MEML.1;
  int MEML.0;

  MEML.0 = MEM <int {0}, &a>;
  MEML.0 = BIT_FIELD_EXPR <MEML.0, 2, 3, 0>;
  MEM <int {0}, &a> = MEML.0;
  MEML.1 = MEM <int {0}, &a>;
  MEML.1 = BIT_FIELD_EXPR <MEML.1, 3, 3, 3>;
  MEM <int {0}, &a> = MEML.1;
  MEML.2 = MEM <int {0}, &a>;
  MEML.2 = BIT_FIELD_EXPR <MEML.2, 8, 17, 8>;
  MEM <int {0}, &a> = MEML.2;
  return;
}


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=35363

[Bug target/35363] Missing bit field coalescing optimization

[rguenth at gcc dot gnu dot org]

------- Comment #5 from rguenth at gcc dot gnu dot org  2008-02-25 18:51 -------
With MEM_REF I get on i686

foo:
        movl    a, %eax
        pushl   %ebp
        movl    %esp, %ebp
        popl    %ebp
        andl    $-33554240, %eax
        orl     $2074, %eax
        movl    %eax, a
        ret
        .size   foo, .-foo
        .p2align 4,,15
.globl bar
        .type   bar, @function
bar:
        movl    a, %eax
        pushl   %ebp
        movl    %esp, %ebp
        popl    %ebp
        andl    $192, %eax
        orl     $1048602, %eax
        movl    %eax, a
        ret

which shows that I made an error in the source ;)


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=35363

[Bug target/35363] Missing bit field coalescing optimization

[rguenth at gcc dot gnu dot org]

------- Comment #4 from rguenth at gcc dot gnu dot org  2008-02-25 18:49 -------
So, the same code should be generated for

union {
struct {
  int b1: 3;
  int b2: 3;
  int b3: 2;
  int b4: 17;
}a;
int b;
} a;
void foo()
{
    a.a.b1 = 2;
    a.a.b2 = 3;
    a.a.b4 = 8;
}
void bar()
{
 a.b = (a.b & (-1u >> (sizeof(a.b)*8 - 2) << 6)) | 2 | (3 << 3) | (8 << 17);
}

modulo errors I made in the bar() case ;)


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=35363

[Bug target/35363] Missing bit field coalescing optimization

[rguenth at gcc dot gnu dot org]

------- Comment #3 from rguenth at gcc dot gnu dot org  2008-02-25 18:44 -------
I would expect the equivalent of

  int tmp = a;
  tmp &= 0x0030;  // fix the mask to be correct, all bits of b3
  tmp |= 2 | 3 | 8; // constant folded and properly shifted
  a = tmp;

I still see three ORs for ppc64 and non-combined rlwimi ops for ppc32.


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=35363