[Bug tree-optimization/46551] New: Generate complex addressing mode CMP instruction in x86-64

[Bug tree-optimization/46551] New: Generate complex addressing mode CMP instruction in x86-64

[adam at consulting dot net.nz]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46551

           Summary: Generate complex addressing mode CMP instruction in
                    x86-64
           Product: gcc
           Version: 4.6.0
            Status: UNCONFIRMED
          Severity: minor
          Priority: P3
         Component: tree-optimization
        AssignedTo: unassigned@gcc.gnu.org
        ReportedBy: adam@consulting.net.nz


Thanks for the improvements in GCC snapshot. Here's a simplified example where
GCC does not emit the instruction cmp (%rsi,%rax,8),%rdx. Instead it generates
mov (%rsi,%rax,8),%rcx; cmp %rdx,%rcx:


#include <stdint.h>

typedef struct {
  int64_t index[2];
  uint64_t cell[16];
} vm_t;

typedef void (*inst_t)(uint32_t *inst, vm_t *vm, uint64_t a);

void branch_upon_complex_compare(uint32_t *inst, vm_t *vm, uint64_t a) {
  if (vm->cell[vm->index[0] - 2] != a) {
    uint64_t dispatch = inst[-1];
    inst -= 1;
    ((inst_t) dispatch)(inst, vm, a);
  } else {
    uint64_t dispatch = inst[1];
    inst += 1;
    ((inst_t) dispatch)(inst, vm, a);
  }
}

int main() {
  return 0;
}


0000000000400480 <branch_upon_complex_compare>:
  400480:       48 8b 06                mov    (%rsi),%rax
  400483:       48 8b 0c c6             mov    (%rsi,%rax,8),%rcx
  400487:       48 39 d1                cmp    %rdx,%rcx
  40048a:       74 0c                   je     400498
<branch_upon_complex_compare+0x18>
  40048c:       8b 47 fc                mov    -0x4(%rdi),%eax
  40048f:       48 83 ef 04             sub    $0x4,%rdi
  400493:       ff e0                   jmpq   *%rax
  400495:       0f 1f 00                nopl   (%rax)
  400498:       8b 47 04                mov    0x4(%rdi),%eax
  40049b:       48 89 ca                mov    %rcx,%rdx
  40049e:       48 83 c7 04             add    $0x4,%rdi
  4004a2:       ff e0                   jmpq   *%rax
  4004a4:       66 66 66 2e 0f 1f 84    nopw   %cs:0x0(%rax,%rax,1)
  4004ab:       00 00 00 00 00 


[I found this inefficient instruction generation while trying to pinpoint an
increase in runtime. I reduced the runtime using asm goto to replace the pair
of instructions with a single complex addressing mode CMP instruction.]

[Bug tree-optimization/46551] Generate complex addressing mode CMP instruction in x86-64

[adam at consulting dot net.nz]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46551

--- Comment #1 from Adam Warner <adam at consulting dot net.nz> 2010-11-19 02:55:18 UTC ---
$ gcc-snapshot.sh --version
gcc (Debian 20101116-1) 4.6.0 20101116 (experimental) [trunk revision 166792]

$ gcc-snapshot.sh -std=gnu99 -O3
complex_addressing_mode_cmp_inst_not_generated.c && objdump -d -m i386:x86-64
a.out

[Bug target/46551] Generate complex addressing mode CMP instruction in x86-64

[dgohman at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46551

Dan Gohman <dgohman at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |dgohman at gmail dot com

--- Comment #2 from Dan Gohman <dgohman at gmail dot com> 2011-06-21 14:26:23 UTC ---
Something has noticed that in the else block, a is equal to the value loaded
from vm->cell[vm->index[0] - 2], so it is replacing the use of a and CSE'ing it
with the loaded value. That's what causes the loaded value to have multiple
uses, which presumably is why GCC subsequently declines to fold the addresssing
into the compare.

[Bug target/46551] Generate complex addressing mode CMP instruction in x86-64

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=46551

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Keywords|                            |missed-optimization
         Resolution|---                         |FIXED
      Known to fail|                            |4.9.0, 5.1.0
             Status|UNCONFIRMED                 |RESOLVED
      Known to work|                            |6.1.0

--- Comment #3 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
GCC 6+ produces:
        movq    (%rsi), %rcx
        movq    %rdi, %rax
        cmpq    %rdx, (%rsi,%rcx,8)
        je      .L2


The difference comes from expand.
GCC 6 produces:
(insn 9 8 10 2 (set (reg:CCZ 17 flags)
        (compare:CCZ (mem:DI (plus:DI (mult:DI (reg:DI 101)
                        (const_int 8 [0x8]))
                    (reg/v/f:DI 99 [ vm ])) [1 vm_3(D)->cell S8 A64])
            (reg/v:DI 100 [ a ]))) /app/example.cpp:12 -1
     (nil))

While GCC 5 produces:
(insn 9 8 10 2 (set (reg:DI 89 [ D.1961 ])
        (mem:DI (plus:DI (mult:DI (reg:DI 101)
                    (const_int 8 [0x8]))
                (reg/v/f:DI 99 [ vm ])) [1 vm_3(D)->cell S8 A64]))
/app/example.cpp:12 -1
     (nil))
(insn 10 9 11 2 (set (reg:CCZ 17 flags)
        (compare:CCZ (reg:DI 89 [ D.1961 ])
            (reg/v:DI 100 [ a ]))) /app/example.cpp:12 -1
     (nil))


I can't find the change that caused this difference though.

[Bug target/46551] Generate complex addressing mode CMP instruction in x86-64

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=46551

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|---                         |6.0