[Bug rtl-optimization/50898] New: Register allocation depends on function return expression on x86 32-bits

[Bug rtl-optimization/50898] New: Register allocation depends on function return expression on x86 32-bits

[izamyatin at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50898

             Bug #: 50898
           Summary: Register allocation depends on function return
                    expression on x86 32-bits
    Classification: Unclassified
           Product: gcc
           Version: 4.7.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: rtl-optimization
        AssignedTo: unassigned@gcc.gnu.org
        ReportedBy: izamyatin@gmail.com


Created attachment 25643
  --> http://gcc.gnu.org/bugzilla/attachment.cgi?id=25643
Testcase

This problem has been noticed during investigation for PR50164.
For attached test case allocator's assignment of registers in some piece of
code depends on how return expression looks like. And it seems that there are
no reasons for this.

For attached case we have following code snippet obtained by fresh compiler:

.L13:
        movzbl  (%esi), %ecx   
        leal    3(%esi), %ebp
        movb    %cl, 48(%esp)
        notb    48(%esp)
        movzbl  1(%esi), %ecx
        movzbl  2(%esi), %ebx
        notl    %ecx
        notl    %ebx
        cmpb    %cl, 48(%esp)
        movl    %ebp, %esi
        movb    %bl, 32(%esp)
        jb      .L18
        cmpb    %cl, 32(%esp)
        movzbl  32(%esp), %ebx
        cmova   %ecx, %ebx
        movl    %ebx, %edi
        jmp     .L10


But if return expression turn to "return 0" we will see following code which is
actually more optimal:

.L13:
        movzbl  (%esi), %edx  <--- edx is used instead of ecx
        leal    3(%esi), %ebp
        movzbl  1(%esi), %ecx
        notl    %edx
        movzbl  2(%esi), %ebx
        notl    %ecx
        notl    %ebx
        cmpb    %cl, %dl
        movl    %ebp, %esi
        movb    %dl, 48(%esp)
        movb    %bl, 32(%esp)
        jb      .L18
        cmpb    %cl, 32(%esp)
        movzbl  32(%esp), %ebx
        cmova   %ecx, %ebx
        movl    %ebx, %edi
        jmp     .L10


 So for some reasons in the first case edx is not used and code contains more
memory instructions.

 gcc -v:
Using built-in specs.
COLLECT_GCC=/export/users/izamyati/compiler/build/bin/gcc
COLLECT_LTO_WRAPPER=/export/users/izamyati/compiler/build/libexec/gcc/x86_64-unknown-linux-gnu/4.7.0/lto-wrapper
Target: x86_64-unknown-linux-gnu
Configured with: ../configure --disable-bootstrap --enable-languages=c,c++
--prefix=/export/users/izamyati/compiler/build/
Thread model: posix
gcc version 4.7.0 20111026 (experimental) (GCC) 

Options for slow code: " -m32  -march=atom -O2 -c"
Options for fast code: " -m32  -march=atom -O2 -DGOOD -c"

[Bug rtl-optimization/50898] Register allocation depends on function return expression on x86 32-bits

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=50898

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
   Target Milestone|---                         |4.8.0
             Status|UNCONFIRMED                 |RESOLVED
      Known to work|                            |4.8.0, 4.9.1

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Looks like it was fixed in GCC 4.8.0