[Bug target/58361] New: Wrong floating point code generated for ARM target

[Bug target/58361] New: Wrong floating point code generated for ARM target

[power at pobox dot sk]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58361

            Bug ID: 58361
           Summary: Wrong floating point code generated for ARM target
           Product: gcc
           Version: 4.7.3
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: power at pobox dot sk

Created attachment 30765
  --> http://gcc.gnu.org/bugzilla/attachment.cgi?id=30765&action=edit
Preprocessed example code

Example code:
-------------
#include <math.h>

static const float LANCE_SPEED = 0.5f;

float posx = 0.0f, posy = 0.0f;
float _deg = 0.0f;

float test(int cnt) {
  float sp;
  if (cnt < 10)
    sp = LANCE_SPEED * cnt / 10;
  else
    sp = LANCE_SPEED;
  float degSin = sin(_deg);
  float degCos = cos(_deg);
  posx += degSin * sp;
  posy += degCos * sp;
  return sp;
}
-------------

Compiling the example code with parameters "-c -O2 -pipe -march=armv7-a
-mcpu=cortex-a8 -mtune=cortex-a8 -mfpu=vfpv3 -mfloat-abi=softfp" generates
wrong code for the case when the input parameter is 10 or more.

The preprocessed source is in the attachment.

The result of "objdump -S -r" is:
-------------
shot2.o:     file format elf32-littlearm


Disassembly of section .text:

00000000 <test>:
   0:    e3500009     cmp    r0, #9
   4:    e92d4010     push    {r4, lr}
   8:    ed2d8b02     vpush    {d8}
   c:    ceb68a00     vmovgt.f32    s16, #96    ; 0x60
  10:    e24dd008     sub    sp, sp, #8
  14:    def27a04     vmovle.f32    s15, #36    ; 0x24
  18:    de080a10     vmovle    s16, r0
  1c:    eeba8aef     vcvt.f32.s32    s16, s16, #1
  20:    de888a27     vdivle.f32    s16, s16, s15
  24:    e59f403c     ldr    r4, [pc, #60]    ; 68 <test+0x68>
  28:    e28d1004     add    r1, sp, #4
  2c:    e1a0200d     mov    r2, sp
  30:    e5940000     ldr    r0, [r4]
  34:    ebfffffe     bl    0 <sincosf>
            34: R_ARM_CALL    sincosf
  38:    edd47a01     vldr    s15, [r4, #4]
  3c:    ed947a02     vldr    s14, [r4, #8]
  40:    eddd6a00     vldr    s13, [sp]
  44:    ee067a88     vmla.f32    s14, s13, s16
  48:    eddd6a01     vldr    s13, [sp, #4]
  4c:    ee180a10     vmov    r0, s16
  50:    ee467a88     vmla.f32    s15, s13, s16
  54:    ed847a02     vstr    s14, [r4, #8]
  58:    edc47a01     vstr    s15, [r4, #4]
  5c:    e28dd008     add    sp, sp, #8
  60:    ecbd8b02     vpop    {d8}
  64:    e8bd8010     pop    {r4, pc}
  68:    00000000     .word    0x00000000
            68: R_ARM_ABS32    .bss
-------------

The instruction at address c assigns the value 0.5f to register s16, and the
instruction at address 1c changes the value in register s16 (but it shouldn't,
in case r0 > 9).

I'm using a GCC crosscompiler for ARM linux (running on x64 linux) - gcc
version 4.7.3.
The result of "gcc -v" is:
-------------
Using built-in specs.
COLLECT_GCC=/opt/pandora/arm-2013.06.10/bin/pandora-gcc
COLLECT_LTO_WRAPPER=/opt/pandora/arm-2013.06.10/bin/../libexec/gcc/arm-cortex_a8-linux-gnueabi/4.7.3/lto-wrapper
Target: arm-cortex_a8-linux-gnueabi
Configured with: /home/roman/toolchain/.build/src/gcc-4.7.3/configure
--build=x86_64-build_unknown-linux-gnu --host=x86_64-build_unknown-linux-gnu
--target=arm-cortex_a8-linux-gnueabi
--prefix=/home/roman/x-tools/arm-cortex_a8-linux-gnueabi
--with-sysroot=/home/roman/x-tools/arm-cortex_a8-linux-gnueabi/arm-cortex_a8-linux-gnueabi/sysroot
--enable-languages=c,c++,d --with-arch=armv7-a --with-cpu=cortex-a8
--with-tune=cortex-a8 --with-fpu=vfpv3 --with-float=softfp
--with-pkgversion='crosstool-NG hg+unknown-20130627.210751'
--enable-__cxa_atexit --disable-libmudflap --disable-libgomp --disable-libssp
--disable-libquadmath --disable-libquadmath-support
--with-gmp=/home/roman/toolchain/.build/arm-cortex_a8-linux-gnueabi/buildtools
--with-mpfr=/home/roman/toolchain/.build/arm-cortex_a8-linux-gnueabi/buildtools
--with-mpc=/home/roman/toolchain/.build/arm-cortex_a8-linux-gnueabi/buildtools
--with-ppl=/home/roman/toolchain/.build/arm-cortex_a8-linux-gnueabi/buildtools
--with-cloog=/home/roman/toolchain/.build/arm-cortex_a8-linux-gnueabi/buildtools
--with-libelf=/home/roman/toolchain/.build/arm-cortex_a8-linux-gnueabi/buildtools
--with-host-libstdcxx='-static-libgcc -Wl,-Bstatic,-lstdc++,-Bdynamic -lm
-L/home/roman/toolchain/.build/arm-cortex_a8-linux-gnueabi/buildtools/lib
-lpwl' --enable-threads=posix --enable-target-optspace --disable-nls
--disable-multilib
--with-local-prefix=/home/roman/x-tools/arm-cortex_a8-linux-gnueabi/arm-cortex_a8-linux-gnueabi/sysroot
--enable-c99 --enable-long-long
Thread model: posix
gcc version 4.7.3 (crosstool-NG hg+unknown-20130627.210751) 
-------------

[Bug target/58361] Wrong floating point code generated for ARM target

[rearnsha at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58361

Richard Earnshaw <rearnsha at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2013-09-09
     Ever confirmed|0                           |1

--- Comment #1 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
Confirmed.  Could also happen on 4.8 or trunk, but this test case won't show
that because of other changes.

[Bug target/58361] Wrong floating point code generated for ARM target

[rearnsha at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58361

--- Comment #2 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
Author: rearnsha
Date: Tue Sep 10 16:46:55 2013
New Revision: 202475

URL: http://gcc.gnu.org/viewcvs?rev=202475&root=gcc&view=rev
Log:
    PR target/58361
    * arm/vfp.md (combine_vcvt_f32_<FCVTI32typename>): Fix pattern to
    support conditional execution.
    (combine_vcvt_f64_<FCVTI32typename>): Likewise.

Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/arm/vfp.md

[Bug target/58361] Wrong floating point code generated for ARM target

[rearnsha at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58361

--- Comment #3 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
Author: rearnsha
Date: Tue Sep 10 16:53:15 2013
New Revision: 202476

URL: http://gcc.gnu.org/viewcvs?rev=202476&root=gcc&view=rev
Log:
    PR target/58361
    * arm/vfp.md (combine_vcvt_f32_<FCVTI32typename>): Fix pattern to
    support conditional execution.
    (combine_vcvt_f64_<FCVTI32typename>): Likewise.

Modified:
    branches/gcc-4_8-branch/gcc/ChangeLog
    branches/gcc-4_8-branch/gcc/config/arm/vfp.md

[Bug target/58361] Wrong floating point code generated for ARM target

[rearnsha at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58361

--- Comment #4 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
Author: rearnsha
Date: Tue Sep 10 16:55:44 2013
New Revision: 202477

URL: http://gcc.gnu.org/viewcvs?rev=202477&root=gcc&view=rev
Log:
    PR target/58361
    * arm/vfp.md (combine_vcvt_f32_<FCVTI32typename>): Fix pattern to
    support conditional execution.
    (combine_vcvt_f64_<FCVTI32typename>): Likewise.

Modified:
    branches/gcc-4_7-branch/gcc/ChangeLog
    branches/gcc-4_7-branch/gcc/config/arm/vfp.md

[Bug target/58361] Wrong floating point code generated for ARM target

[rearnsha at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58361

Richard Earnshaw <rearnsha at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Keywords|                            |wrong-code
             Status|NEW                         |RESOLVED
         Resolution|---                         |FIXED
   Target Milestone|---                         |4.7.4

--- Comment #5 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
Fixed