[Bug target/61330] New: Thumb ICE for case 920507-1.c

[Bug target/61330] New: Thumb ICE for case 920507-1.c

[tony.wang at arm dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61330

            Bug ID: 61330
           Summary: Thumb ICE for case 920507-1.c
           Product: gcc
           Version: 4.10.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: tony.wang at arm dot com

I'm running regression test for the latest GCC trunk for cortex-m0, I run into
below ICE, but after I remove the commit at trunk@210901, the test case will
pass.

How to reproduce:
Executing on host: /work/terguo01/trunk-t1/build-native/gcc-final/gcc/xgcc
-B/work/terguo01/trunk-t1/build-native/gcc-final/gcc/
/work/terguo01/trunk-t1/src/gcc/gcc/testsuite/gcc.dg/noncompile/920507-1.c 
-fno-diagnostics-show-caret -fdiagnostics-color=never   -O1  -ffat-lto-objects
-S    -mthumb -mcpu=cortex-m0 -o 920507-1.s    (timeout = 300)
spawn /work/terguo01/trunk-t1/build-native/gcc-final/gcc/xgcc
-B/work/terguo01/trunk-t1/build-native/gcc-final/gcc/
/work/terguo01/trunk-t1/src/gcc/gcc/testsuite/gcc.dg/noncompile/920507-1.c
-fno-diagnostics-show-caret -fdiagnostics-color=never -O1 -ffat-lto-objects -S
-mthumb -mcpu=cortex-m0 -o 920507-1.s^M
/work/terguo01/trunk-t1/src/gcc/gcc/testsuite/gcc.dg/noncompile/920507-1.c: In
function 'x':^M
/work/terguo01/trunk-t1/src/gcc/gcc/testsuite/gcc.dg/noncompile/920507-1.c:5:16:
error: invalid register name for 'a'^M
/work/terguo01/trunk-t1/src/gcc/gcc/testsuite/gcc.dg/noncompile/920507-1.c:3:1:
internal compiler error: in symtab_get_node, at cgraph.h:1021^M
0xc1920c symtab_get_node^M
        /work/terguo01/trunk-t1/src/gcc/gcc/cgraph.h:1018^M
0xc1920c symtab_get_node^M
        /work/terguo01/trunk-t1/src/gcc/gcc/varasm.c:1134^M
0xc1920c decl_comdat_group^M
        /work/terguo01/trunk-t1/src/gcc/gcc/cgraph.h:1629^M
0xc1920c get_block_for_decl^M
        /work/terguo01/trunk-t1/src/gcc/gcc/varasm.c:1146^M
0xc1cadf make_decl_rtl(tree_node*)^M
        /work/terguo01/trunk-t1/src/gcc/gcc/varasm.c:1376^M
0x8d6b4f rest_of_decl_compilation(tree_node*, int, int)^M
        /work/terguo01/trunk-t1/src/gcc/gcc/passes.c:215^M
0x6206a3 expand_one_hard_reg_var^M
        /work/terguo01/trunk-t1/src/gcc/gcc/cfgexpand.c:1108^M
0x6206a3 expand_one_var^M
        /work/terguo01/trunk-t1/src/gcc/gcc/cfgexpand.c:1295^M
0x620e0b expand_used_vars_for_block^M
        /work/terguo01/trunk-t1/src/gcc/gcc/cfgexpand.c:1338^M
0x62c1e6 expand_used_vars^M

[Bug target/61330] [4.10 Regression] Thumb ICE for case 920507-1.c

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61330

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Keywords|                            |ice-on-invalid-code
   Target Milestone|---                         |4.10.0
            Summary|Thumb ICE for case          |[4.10 Regression] Thumb ICE
                   |920507-1.c                  |for case 920507-1.c

--- Comment #1 from Richard Biener <rguenth at gcc dot gnu.org> ---
Seems the parser fails to set DECL_HARD_REGISTER on that bogus decl.

[Bug target/61330] [4.10 Regression] Thumb ICE for case 920507-1.c

[jgreenhalgh at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61330

jgreenhalgh at gcc dot gnu.org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |schwab@linux-m68k.org

--- Comment #2 from jgreenhalgh at gcc dot gnu.org ---
*** Bug 61394 has been marked as a duplicate of this bug. ***

[Bug target/61330] [4.10 Regression] Thumb ICE for case 920507-1.c

[jgreenhalgh at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61330

jgreenhalgh at gcc dot gnu.org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Target|                            |aarch64*-*-*, arm*-*-*,
                   |                            |powerpc*-*-*
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2014-06-05
                 CC|                            |jgreenhalgh at gcc dot gnu.org
     Ever confirmed|0                           |1

--- Comment #3 from jgreenhalgh at gcc dot gnu.org ---
Confirmed across aarch64* and arm*.

[Bug target/61330] [4.10 Regression] Thumb ICE for case 920507-1.c

[tony.wang at arm dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61330

--- Comment #5 from wangzheyu <tony.wang at arm dot com> ---
(In reply to Richard Biener from comment #1)
> Seems the parser fails to set DECL_HARD_REGISTER on that bogus decl.
Hi Richard,
I find that in function make_decl_rtl(gcc/varasm.c:1357), there's one line
comment: 
/* As a register variable, it has no section.  */

And for the correct reigster type declaration like: register int *a asm(“r1”),
the program will just directly return(gcc/varasm.c:1358), and won't sink into
the symbol ref generation part. So symtab_get_node won't be called.

It seems to be a long time for the invalid register type declaration to be sink
into the symbol ref generation part of function make_decl_rtl, which will also
lead to wrong rtx generation.
register int *a asm("r1")=>(reg:SI 1 r1 [orig:0 a] [0])
register int *a asm("unknown register")=>(symbol_ref:SI ("unknown register")
[flag 0x80])
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From: "kyukhin at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug tree-optimization/61742] [4.10 Regression] wrong code at -O3 on x86_64-linux-gnu
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https://gcc.gnu.org/bugzilla/show_bug.cgi?ida742

--- Comment #5 from Kirill Yukhin <kyukhin at gcc dot gnu.org> ---
Author: kyukhin
Date: Thu Jul 10 07:38:39 2014
New Revision: 212421

URL: https://gcc.gnu.org/viewcvs?rev!2421&root=gcc&view=rev
Log:
PR tree-optimization/61742

gcc/testsuite/
        * gcc.dg/torture/pr61742.c: New test.
        * gcc.gg/vect/cond-reduc-1.c: Rename it to vect-cond-reduc-1.c
        * gcc.gg/vect/cond-reduc-2.c: Rename it to vect-cond-reduc-2.c


Added:
    trunk/gcc/testsuite/gcc.dg/torture/pr61742.c
    trunk/gcc/testsuite/gcc.dg/vect/vect-cond-reduc-1.c
    trunk/gcc/testsuite/gcc.dg/vect/vect-cond-reduc-2.c
Removed:
    trunk/gcc/testsuite/gcc.dg/vect/cond-reduc-1.c
    trunk/gcc/testsuite/gcc.dg/vect/cond-reduc-2.c
Modified:
    trunk/gcc/testsuite/ChangeLog

[Bug target/61330] [4.10 Regression] Thumb ICE for case 920507-1.c

[tony.wang at arm dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61330

--- Comment #6 from wangzheyu <tony.wang at arm dot com> ---
Posted a possible fix for this bug:
https://gcc.gnu.org/ml/gcc-patches/2014-07/msg01938.html

[Bug target/61330] [5 Regression] Thumb ICE for case 920507-1.c

[jsm28 at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61330

--- Comment #7 from Joseph S. Myers <jsm28 at gcc dot gnu.org> ---
Author: jsm28
Date: Tue Aug 26 17:06:31 2014
New Revision: 214526

URL: https://gcc.gnu.org/viewcvs?rev=214526&root=gcc&view=rev
Log:
Fix ARM ICE for register var asm ("pc") (PR target/60606).

    PR target/60606
    PR target/61330
    * varasm.c (make_decl_rtl): Clear DECL_ASSEMBLER_NAME and
    DECL_HARD_REGISTER and return for invalid register specifications.
    * cfgexpand.c (expand_one_var): If expand_one_hard_reg_var clears
    DECL_HARD_REGISTER, call expand_one_error_var.
    * config/arm/arm.c (arm_hard_regno_mode_ok): Do not allow
    CC_REGNUM with non-MODE_CC modes.
    (arm_regno_class): Return NO_REGS for PC_REGNUM.

testsuite:
    * gcc.dg/torture/pr60606-1.c, gcc.target/arm/pr60606-2.c,
    gcc.target/arm/pr60606-3.c, gcc.target/arm/pr60606-4.c: New tests.

Added:
    trunk/gcc/testsuite/gcc.dg/torture/pr60606-1.c
    trunk/gcc/testsuite/gcc.target/arm/pr60606-2.c
    trunk/gcc/testsuite/gcc.target/arm/pr60606-3.c
    trunk/gcc/testsuite/gcc.target/arm/pr60606-4.c
Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/cfgexpand.c
    trunk/gcc/config/arm/arm.c
    trunk/gcc/testsuite/ChangeLog
    trunk/gcc/varasm.c

[Bug target/61330] [5 Regression] Thumb ICE for case 920507-1.c

[jsm28 at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61330

Joseph S. Myers <jsm28 at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |RESOLVED
         Resolution|---                         |FIXED

--- Comment #8 from Joseph S. Myers <jsm28 at gcc dot gnu.org> ---
Fixed for GCC 5.

[Bug target/61330] [5 Regression] Thumb ICE for case 920507-1.c

[yroux at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61330

--- Comment #9 from Yvan Roux <yroux at gcc dot gnu.org> ---
Author: yroux
Date: Wed Sep  3 07:23:01 2014
New Revision: 214847

URL: https://gcc.gnu.org/viewcvs?rev=214847&root=gcc&view=rev
Log:
gcc/
2014-09-03  Yvan Roux  <yvan.roux@linaro.org>

    Backport from trunk r214526.
    2014-08-26  Joseph Myers  <joseph@codesourcery.com>

    PR target/60606
    PR target/61330
    * varasm.c (make_decl_rtl): Clear DECL_ASSEMBLER_NAME and
    DECL_HARD_REGISTER and return for invalid register specifications.
    * cfgexpand.c (expand_one_var): If expand_one_hard_reg_var clears
    DECL_HARD_REGISTER, call expand_one_error_var.
    * config/arm/arm.c (arm_hard_regno_mode_ok): Do not allow
    CC_REGNUM with non-MODE_CC modes.
    (arm_regno_class): Return NO_REGS for PC_REGNUM.

gcc/testsuite/
2014-09-03  Yvan Roux  <yvan.roux@linaro.org>

    Backport from trunk r214526.
    2014-08-26  Joseph Myers  <joseph@codesourcery.com>

    PR target/60606
    PR target/61330
    * gcc.dg/torture/pr60606-1.c, gcc.target/arm/pr60606-2.c,
    gcc.target/arm/pr60606-3.c, gcc.target/arm/pr60606-4.c: New tests.


Added:
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.dg/torture/pr60606-1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/pr60606-2.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/pr60606-3.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/pr60606-4.c
Modified:
    branches/linaro/gcc-4_9-branch/gcc/ChangeLog.linaro
    branches/linaro/gcc-4_9-branch/gcc/cfgexpand.c
    branches/linaro/gcc-4_9-branch/gcc/config/arm/arm.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/ChangeLog.linaro
    branches/linaro/gcc-4_9-branch/gcc/varasm.c