[Bug target/66866] New: [miscompile] incorrect load address on manual vector shuffle

[Bug target/66866] New: [miscompile] incorrect load address on manual vector shuffle

[kretz at kde dot org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66866

            Bug ID: 66866
           Summary: [miscompile] incorrect load address on manual vector
                    shuffle
           Product: gcc
           Version: 5.1.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: kretz at kde dot org
  Target Milestone: ---

The following testcase fails at -O2:

#include <xmmintrin.h>
typedef short A __attribute__((__may_alias__));
short extr(const __m128i &d, int index) { return reinterpret_cast<const A
*>(&d)[index]; }
A &extr(__m128i &d, int index) { return reinterpret_cast<A *>(&d)[index]; }
__m128i shuf(const __m128i v)
{
  __m128i r;
  for (int i = 0; i + 4 <= 8; i += 4) {
    extr(r, i + 0) = extr(v, i + 1);
    extr(r, i + 1) = extr(v, i + 0);
    extr(r, i + 2) = extr(v, i + 3);
    extr(r, i + 3) = extr(v, i + 2);
  }
  return r;
}
int main()
{
  __attribute__((aligned(16))) short mem[8];
  *reinterpret_cast<__m128i *>(mem) = shuf(_mm_setr_epi16(0, 1, 2, 3, 4, 5, 6,
7));
  if (mem[0] == 1 && mem[1] == 0 && mem[2] == 3 && mem[3] == 2 && mem[4] == 5
&&
      mem[5] == 0 && mem[6] == 7 && mem[7] == 6) {
    abort();
  }
  return 0;
}

Here's a little survey:
for CXX in /opt/*/bin/{g++,clang++}; do echo -n "$CXX: "; $CXX -O2 testcase.cpp
&& ./a.out && echo passed || echo failed; done
/opt/gcc-4.5.2/bin/g++: passed
/opt/gcc-4.5.3/bin/g++: passed
/opt/gcc-4.5.4/bin/g++: passed
/opt/gcc-4.6.0/bin/g++: passed
/opt/gcc-4.6.1/bin/g++: passed
/opt/gcc-4.6.3/bin/g++: passed
/opt/gcc-4.7.0/bin/g++: failed
/opt/gcc-4.7.1/bin/g++: failed
/opt/gcc-4.7.2/bin/g++: failed
/opt/gcc-4.8.0/bin/g++: failed
/opt/gcc-4.8.2/bin/g++: failed
/opt/gcc-4.9.0/bin/g++: failed
/opt/gcc-4.9.1/bin/g++: failed
/opt/gcc-5.1.0/bin/g++: failed
/opt/gcc-6-snapshot/bin/g++: failed
/opt/clang-3.2/bin/clang++: passed
/opt/clang-3.3/bin/clang++: passed
/opt/clang-3.4/bin/clang++: passed
/opt/clang-3.5/bin/clang++: passed
/opt/clang-3.6/bin/clang++: passed
/opt/clang-master/bin/clang++: passed

The value at index 5 is assigned incorrectly from v[0] instead of v[4]. The
issue goes away if I manually unroll the loop.

[Bug target/66866] [miscompile] incorrect load address on manual vector shuffle

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66866

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2015-07-14
     Ever confirmed|0                           |1

--- Comment #1 from Richard Biener <rguenth at gcc dot gnu.org> ---
The gimple looks ok to me:

__m128i shuf(__m128i) (const __m128i v)
{
  __m128i r;
  __m128i _16;
...
  <bb 2>:
  _43 = MEM[(const A * {ref-all})&v + 2B];
  MEM[(A & {ref-all})&r] = _43;
  _47 = MEM[(const A * {ref-all})&v];
  MEM[(A & {ref-all})&r + 2] = _47;
  _57 = MEM[(const A * {ref-all})&v + 6B];
  MEM[(A & {ref-all})&r + 4] = _57;
  _61 = MEM[(const A * {ref-all})&v + 4B];
  MEM[(A & {ref-all})&r + 6] = _61;
  _73 = MEM[(const A * {ref-all})&v + 10B];
  MEM[(A & {ref-all})&r + 8] = _73;
  _77 = MEM[(const A * {ref-all})&v + 8B];
  MEM[(A & {ref-all})&r + 10] = _77;
  _87 = MEM[(const A * {ref-all})&v + 14B];
  MEM[(A & {ref-all})&r + 12] = _87;
  _91 = MEM[(const A * {ref-all})&v + 12B];
  MEM[(A & {ref-all})&r + 14] = _91;
  _16 = r;
  r ={v} {CLOBBER};
  return _16;

The assembler is slightly convoluted:

_Z4shufDv2_x:
.LFB527:
        .cfi_startproc
        movaps  %xmm0, -24(%rsp)
        movq    %xmm0, %rax
        movd    %xmm0, %edx
        pxor    %xmm0, %xmm0
        sarl    $16, %edx
        pinsrw  $0, %edx, %xmm0
        movq    %rax, %rdx
        sarq    $48, %rdx
        salq    $16, %rax
        sarq    $48, %rax
        pinsrw  $1, -24(%rsp), %xmm0
        pinsrw  $2, %edx, %xmm0
        pinsrw  $3, %eax, %xmm0
        movq    -16(%rsp), %rax
        movl    %eax, %edx
        sarl    $16, %edx
        pinsrw  $4, %edx, %xmm0
        movq    %rax, %rdx
        salq    $16, %rax
        sarq    $48, %rdx
        sarq    $48, %rax
        pinsrw  $5, -24(%rsp), %xmm0
        pinsrw  $6, %edx, %xmm0
        pinsrw  $7, %eax, %xmm0
        ret

but the duplicate -24(%rsp) source in the pinsrw instructions looks
suspicious indeed.

Manually unrolling only inlines the function, the function itself is
still miscompiled the same way.

Reduced testcase:

#include <xmmintrin.h>
typedef short A __attribute__((__may_alias__));
short extr(const __m128i &d, int index) { return reinterpret_cast<const A
*>(&d)[index]; }
A &extr(__m128i &d, int index) { return reinterpret_cast<A *>(&d)[index]; }
__m128i __attribute__((noinline))
shuf(const __m128i v)
{
  __m128i r;
  extr(r, 5) = extr(v, 4);
  return r;
}
int main()
{
  __attribute__((aligned(16))) short mem[8];
  *reinterpret_cast<__m128i *>(mem) = shuf(_mm_setr_epi16(0, 1, 2, 3, 4, 5, 6,
7));
  if (mem[5] != 4)
    abort ();
  return 0;
}

[Bug target/66866] [miscompile] incorrect load address on manual vector shuffle

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66866

--- Comment #2 from Richard Biener <rguenth at gcc dot gnu.org> ---
More reduced, fails at -O1:

extern "C" void abort (void);
typedef long long __m128i __attribute__ ((__vector_size__ (16),
__may_alias__));
typedef short A __attribute__((__may_alias__));
__m128i __attribute__((noinline))
shuf(const __m128i v)
{
  __m128i r;
  reinterpret_cast<A *>(&r)[5] = reinterpret_cast<const A *>(&v)[4];
  return r;
}
int main()
{
  __attribute__((aligned(16))) short mem[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
  *reinterpret_cast<__m128i *>(mem) = shuf (*reinterpret_cast<__m128i *>(mem));
  if (mem[5] != 4)
    abort ();
  return 0;
}


_Z4shufDv2_x:
.LFB527:
        .cfi_startproc
        movaps  %xmm0, -24(%rsp)
        pxor    %xmm0, %xmm0
        pinsrw  $5, -24(%rsp), %xmm0
        ret

[Bug target/66866] [miscompile] incorrect load address on manual vector shuffle

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66866

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Keywords|                            |wrong-code
             Target|                            |x86_64-*-*
                 CC|                            |uros at gcc dot gnu.org

--- Comment #3 from Richard Biener <rguenth at gcc dot gnu.org> ---
Expansion is already wrong:

;; MEM[(A * {ref-all})&r + 10B] = _2;

(insn 6 5 7 (set (reg:TI 92)
        (subreg:TI (reg/v:V2DI 91 [ v ]) 0)) t.c:8 -1
     (nil))

(insn 7 6 8 (set (reg:V8HI 93)
        (vec_merge:V8HI (vec_duplicate:V8HI (subreg:HI (reg:TI 92) 0))
            (subreg:V8HI (reg/v:V2DI 89 [ r ]) 0)
            (const_int 32 [0x20]))) t.c:8 -1
     (nil))

(insn 8 7 0 (set (reg/v:V2DI 89 [ r ])
        (subreg:V2DI (reg:V8HI 93) 0)) t.c:8 -1
     (nil))

(subreg:HI (reg:TI 92) 0) selects the wrong source.

We go

        /* In cases where an aligned union has an unaligned object
           as a field, we might be extracting a BLKmode value from
           an integer-mode (e.g., SImode) object.  Handle this case
           by doing the extract into an object as wide as the field
           (which we know to be the width of a basic mode), then
           storing into memory, and changing the mode to BLKmode.  */
        if (mode1 == VOIDmode
...
            op0 = extract_bit_field (op0, bitsize, bitpos, unsignedp,
                                     (modifier == EXPAND_STACK_PARM
                                      ? NULL_RTX : target),
                                     ext_mode, ext_mode);
(gdb) p debug_rtx (op0)
(reg/v:V2DI 91 [ v ])
(gdb) p bitsize
$7 = 16
(gdb) p bitpos
$8 = 64
(gdb) p ext_mode
$9 = HImode

which gets us

(gdb) p debug_rtx (op0)
(subreg:HI (reg:TI 92) 8)

so handling the load is fine.  Ultimately returned to

#0  0x0000000000c1bf17 in store_field (target=0x7ffff6a49d80, bitsize=16, 
    bitpos=80, bitregion_start=80, bitregion_end=95, mode=HImode, 
    exp=<ssa_name 0x7ffff68d5b40>, alias_set=0, nontemporal=false)
    at /space/rguenther/tramp3d/trunk/gcc/expr.c:6643
#1  0x0000000000c1582a in expand_assignment (to=<mem_ref 0x7ffff6a42168>, 
    from=<ssa_name 0x7ffff68d5b40>, nontemporal=false)
    at /space/rguenther/tramp3d/trunk/gcc/expr.c:5016

and leading to

#0  store_bit_field_1 (str_rtx=0x7ffff6a49d80, bitsize=16, bitnum=80, 
    bitregion_start=80, bitregion_end=95, fieldmode=HImode, 
    value=0x7ffff6a49f18, fallback_p=true)
    at /space/rguenther/tramp3d/trunk/gcc/expmed.c:881
876       /* If OP0 is a multi-word register, narrow it to the affected word.
877          If the region spans two words, defer to store_split_bit_field.  */
878       if (!MEM_P (op0) && GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
879         {

and finally using the insv path.

Breakpoint 7, store_bit_field_using_insv (insv=0x7fffffffd380, 
    op0=0x7ffff6a49f48, bitsize=16, bitnum=16, value=0x7ffff6a49f18)
    at /space/rguenther/tramp3d/trunk/gcc/expmed.c:508
508       rtx xop0 = op0;
(gdb) p debug_rtx (op0)
(subreg:DI (reg/v:V2DI 89 [ r ]) 8)
$40 = void
(gdb) p debug_rtx (value)
(subreg:HI (reg:TI 92) 8)
$41 = void

creating insv with

611       create_fixed_operand (&ops[0], xop0);
612       create_integer_operand (&ops[1], bitsize);
613       create_integer_operand (&ops[2], bitnum);
614       create_input_operand (&ops[3], value1, op_mode);
(gdb) p debug_rtx (xop0)
(subreg:DI (reg/v:V2DI 89 [ r ]) 8)
$47 = void
(gdb) p debug_rtx (value1)
(subreg:DI (reg:TI 92) 8)
$48 = void
(gdb) p bitsize
$49 = 16
(gdb) p bitnum
$50 = 16

[Bug target/66866] [miscompile] incorrect load address on manual vector shuffle

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66866

--- Comment #4 from Richard Biener <rguenth at gcc dot gnu.org> ---
bool
ix86_expand_pinsr (rtx *operands)
{
...
  if (GET_CODE (src) == SUBREG)
    src = SUBREG_REG (src);

and lost SUBREG_OFFSET.

[Bug target/66866] [miscompile] incorrect load address on manual vector shuffle

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66866

--- Comment #5 from Richard Biener <rguenth at gcc dot gnu.org> ---
"Safe" fix:

Index: gcc/config/i386/i386.c
===================================================================
--- gcc/config/i386/i386.c      (revision 225768)
+++ gcc/config/i386/i386.c      (working copy)
@@ -50528,7 +50528,11 @@ ix86_expand_pinsr (rtx *operands)
     }

   if (GET_CODE (src) == SUBREG)
-    src = SUBREG_REG (src);
+    {
+      if (SUBREG_BYTE (src) != 0)
+       return false;
+      src = SUBREG_REG (src);
+    }

   switch (GET_MODE (dst))
     {

but with awful consequences for code-generation (-O2, for the reduced
testcase):

_Z4shufDv2_x:
.LFB0:
        .cfi_startproc
        pxor    %xmm1, %xmm1
        movabsq $-4294901761, %rdx
        movaps  %xmm0, -24(%rsp)
        movq    -16(%rsp), %rax
        movaps  %xmm1, -24(%rsp)
        movzwl  %ax, %eax
        salq    $16, %rax
        movq    -16(%rsp), %rcx
        andq    %rcx, %rdx
        orq     %rax, %rdx
        movq    %rdx, -16(%rsp)
        movdqa  -24(%rsp), %xmm0
        ret

[Bug target/66866] [miscompile] incorrect load address on manual vector shuffle

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66866

Uroš Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |ASSIGNED
                 CC|uros at gcc dot gnu.org            |
           Assignee|unassigned at gcc dot gnu.org      |ubizjak at gmail dot com

--- Comment #6 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Richard Biener from comment #5)
> "Safe" fix:

No, no... pextr to a temporary should be used here.

I plan to introduce pextr handling to "insv<mode>" pattern. Then,
ix86_expand_pinsr will call ix86_expand_pextr for non-lowpart src subregs (and
in a similar way, new ix86_expand_pextr will call ix86_expand_pinsr for
non-lowpart dst subregs).
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Subject: [Bug target/66866] [miscompile] incorrect load address on manual vector shuffle
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66866

--- Comment #7 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Uroš Bizjak from comment #6)
> (In reply to Richard Biener from comment #5)
> > "Safe" fix:
> 
> No, no... pextr to a temporary should be used here.
> 
> I plan to introduce pextr handling to "insv<mode>" pattern. Then,

... "extzv<mode>" pattern.
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https://gcc.gnu.org/bugzilla/show_bug.cgi?idf872

Marek Polacek <mpolacek at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |mpolacek at gcc dot gnu.org

--- Comment #3 from Marek Polacek <mpolacek at gcc dot gnu.org> ---
This ought to be easy to do in match.pd, but I'm not sure if this
transformation is beneficial for other architectures as well (it doesn't seem
to reduce the number of operations).

[Bug target/66866] [miscompile] incorrect load address on manual vector shuffle

[uros at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66866

--- Comment #8 from uros at gcc dot gnu.org ---
Author: uros
Date: Wed Jul 15 22:20:17 2015
New Revision: 225852

URL: https://gcc.gnu.org/viewcvs?rev=225852&root=gcc&view=rev
Log:
        PR target/66866
        * config/i386/i386-protos.h (ix86_expand_pextr): New prototype.
        * config/i386/i386.c (ix86_expand_pextr): New function.
        (ix86_expand_pinsr): Handle V1TI and TI modes.  Call ix86_expand_pextr
        for non-lowpart subregs.
        * config/i386/i386.md (extzv<mode>): Expand with ix86_expand_pextr.
        (insv<mode>): Use SWI248 mode iterator.
        (insv<mode>_1): Ditto.

testsuite/ChangeLog:

        PR target/66866
        * g++.dg/pr66866.C: New test.


Added:
    trunk/gcc/testsuite/g++.dg/pr66866.C
Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/i386/i386-protos.h
    trunk/gcc/config/i386/i386.c
    trunk/gcc/config/i386/i386.md
    trunk/gcc/testsuite/ChangeLog

[Bug target/66866] [4.9/5 Regression] incorrect load address on manual vector shuffle

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66866

Uroš Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|---                         |4.9.4
            Summary|[miscompile] incorrect load |[4.9/5 Regression]
                   |address on manual vector    |incorrect load address on
                   |shuffle                     |manual vector shuffle

--- Comment #9 from Uroš Bizjak <ubizjak at gmail dot com> ---
Fixed in mainline.

The reduced testcase now compiles to:

_Z4shufDv2_x:
.LFB0:
        .cfi_startproc
        vpextrw $4, %xmm0, %eax
        vpxor   %xmm0, %xmm0, %xmm0
        vpinsrw $5, %eax, %xmm0, %xmm0
        ret

Patch needs backports to release branches.
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https://gcc.gnu.org/bugzilla/show_bug.cgi?idf890

--- Comment #1 from Andi Kleen <andi-gcc at firstfloor dot org> ---

The problem seems to be that
bb-reorder.c:find_rarely_executed_basic_blocks_and_crossing_edges
returns no edges without profile feedback, which prevents generation of a
section split note.

[Bug target/66866] [4.9/5 Regression] incorrect load address on manual vector shuffle

[uros at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66866

--- Comment #10 from uros at gcc dot gnu.org ---
Author: uros
Date: Fri Jul 17 20:25:09 2015
New Revision: 225968

URL: https://gcc.gnu.org/viewcvs?rev=225968&root=gcc&view=rev
Log:
        PR target/66866
        * config/i386/i386.c (ix86_expand_pinsr): Reject non-lowpart
        source subregs.

testsuite/ChangeLog:

        PR target/66866
        * g++.dg/pr66866.C: New test.


Added:
    branches/gcc-5-branch/gcc/testsuite/g++.dg/pr66866.C
Modified:
    branches/gcc-5-branch/gcc/ChangeLog
    branches/gcc-5-branch/gcc/config/i386/i386.c
    branches/gcc-5-branch/gcc/testsuite/ChangeLog

[Bug target/66866] [4.9/5 Regression] incorrect load address on manual vector shuffle

[uros at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66866

--- Comment #11 from uros at gcc dot gnu.org ---
Author: uros
Date: Fri Jul 17 21:39:27 2015
New Revision: 225970

URL: https://gcc.gnu.org/viewcvs?rev=225970&root=gcc&view=rev
Log:
        PR target/66866
        * config/i386/i386.c (ix86_expand_pinsr): Reject non-lowpart
        source subregs.

testsuite/ChangeLog:

        PR target/66866
        * g++.dg/pr66866.C: New test.


Added:
    branches/gcc-4_9-branch/gcc/testsuite/g++.dg/pr66866.C
Modified:
    branches/gcc-4_9-branch/gcc/ChangeLog
    branches/gcc-4_9-branch/gcc/config/i386/i386.c
    branches/gcc-4_9-branch/gcc/testsuite/ChangeLog

[Bug target/66866] [4.9/5 Regression] incorrect load address on manual vector shuffle

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66866

Uroš Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Target|x86_64-*-*                  |x86
             Status|ASSIGNED                    |RESOLVED
         Resolution|---                         |FIXED

--- Comment #12 from Uroš Bizjak <ubizjak at gmail dot com> ---
Fixed everywhere.
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From: "jan.smets@alcatel-lucent.com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug middle-end/66920] New: ICE in expand_debug_locations, at cfgexpand.c:3826
Date: Fri, 17 Jul 2015 21:43:00 -0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?idf920

            Bug ID: 66920
           Summary: ICE in expand_debug_locations, at cfgexpand.c:3826
           Product: gcc
           Version: 4.8.2
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: middle-end
          Assignee: unassigned at gcc dot gnu.org
          Reporter: jan.smets@alcatel-lucent.com
  Target Milestone: ---

Compile with  -xc++ -w   -m32 -gdwarf-4  -mno-sse -O1  test.cpp



test.cpp: In function 'bool test_sp(Desc*, data*)':
test.cpp:29:1: internal compiler error: in expand_debug_locations, at
cfgexpand.c:3826
 test_sp(Desc *pDesc, data *info) {


typedef long int64_t;
typedef int UINT32;
typedef short len;
struct header;
typedef UINT32 number;
struct Desc {
  short length;
};
typedef int64_t v2di __attribute__((vector_size(16)));
int table;
struct data;


void __attribute__((__always_inline__))
counter_inc(struct counter *, long, long) {
  v2di v2di{};
}

bool ing_build_qhdr_and_output(Desc *pDesc,
                                   data *, header *,
                                   number, number, bool,
                                   len, len,
                                   len) {
  counter_inc((counter *)table, 1,
                  pDesc->length);
}

bool __attribute__((target("sse4.2")))
test_sp(Desc *pDesc, data *info) {
  number dest, queue_stat_addr, plen_length;
  UINT32 offset;
  UINT32 extra_header_size;
  header *sw_hdr;
  return ing_build_qhdr_and_output(pDesc, info, sw_hdr, dest,
                                       queue_stat_addr, 2, offset,
                                       extra_header_size, plen_length);
}