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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug rtl-optimization/87763] [9/10 Regression] aarch64 target testcases fail after r265398
Date: Sat, 04 Apr 2020 17:24:24 +0000	[thread overview]
Message-ID: <bug-87763-4-De9g1MakUx@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-87763-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87763

--- Comment #68 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(In reply to rsandifo@gcc.gnu.org from comment #62)
> For the two bfi ones: are we really sure that the old code is better?
> It's a difference between a MOV and a BFI or an AND and an ORR.
> The BFI wins (at least for code-size) if we need the same MOV
> for something else.  But the AND/ORR sequence wins in high register
> pressure, since it only needs one register rather than two.

On some processors (ThunderX2 and OcteonTX2 and maybe others [I have not looked
into all of the micro-arches there are]), the mov/bfi case is most likely
better as the mov is removed during renaming phase and not actually issued so
it will turn into just one instruction in a latency of 1 rather than 2
instructions and latency of 2.

  parent reply	other threads:[~2020-04-04 17:24 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <bug-87763-4@http.gcc.gnu.org/bugzilla/>
2020-03-12 11:58 ` jakub at gcc dot gnu.org
2020-04-04 17:24 ` pinskia at gcc dot gnu.org [this message]
2021-04-09 12:43 ` [Bug rtl-optimization/87763] [9/10/11 " cvs-commit at gcc dot gnu.org
2021-04-09 12:59 ` rsandifo at gcc dot gnu.org
2022-05-06  8:30 ` [Bug rtl-optimization/87763] [9/10/11/12/13 " jakub at gcc dot gnu.org
2023-05-08 12:21 ` [Bug rtl-optimization/87763] [10/11/12/13/14 Regression] aarch64 target testcases fail after r265398 (gcc.target/aarch64/insv_1.c left) rguenth at gcc dot gnu.org

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