[Bug tree-optimization/94092] Code size and performance degradations after -ftree-loop-distribute-patterns was enabled at -O[2s]+

["rguenther at suse dot de" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94092

--- Comment #15 from rguenther at suse dot de <rguenther at suse dot de> ---
On Fri, 30 Apr 2021, law at gcc dot gnu.org wrote:

> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94092
> 
> Jeffrey A. Law <law at gcc dot gnu.org> changed:
> 
>            What    |Removed                     |Added
> ----------------------------------------------------------------------------
>                  CC|                            |law at gcc dot gnu.org
> 
> --- Comment #14 from Jeffrey A. Law <law at gcc dot gnu.org> ---
> WRT Jim's comment about alignments in c#6.
> 
> Right now a pointer's alignment is really only used to eliminate unnecessary
> masking -- we don't propagate a pointer's known alignment to improve the known
> alignment of memory operations involving that pointer.

Hmm, but we do - in set_mem_attributes_minus_bitpos.  But maybe below
is for way later RTL generation,

> This is something I'd cobbled together for a closely related issue which will
> try to increase the known alignment of a MEM by using the alignment of a
> pointer to that MEM.
> 
> We've gone a slightly different (and more effective) route for that internal
> issue, but this may still be worth polishing a bit and submitting.
> 
> diff --git a/gcc/emit-rtl.c b/gcc/emit-rtl.c
> index 972512e81..be9ff76b5 100644
> --- a/gcc/emit-rtl.c
> +++ b/gcc/emit-rtl.c
> @@ -859,6 +859,28 @@ gen_rtx_MEM (machine_mode mode, rtx addr)
>       we clear it here.  */
>    MEM_ATTRS (rt) = 0;
> 
> +  /* If we can deduce a higher alignment for the memory access
> +     based on the pointer, then it's advantageous to do so.   */
> +  unsigned int align = 0;
> +  if (REG_P (addr)
> +      && REG_POINTER (addr))
> +    align = REGNO_POINTER_ALIGN (REGNO (addr));
> +  else if (GET_CODE (addr) == PLUS
> +          && REG_P (XEXP (addr, 0))
> +          && REG_POINTER (XEXP (addr, 0))
> +          && REGNO_POINTER_ALIGN (REGNO (XEXP (addr, 0)))
> +          && GET_CODE (XEXP (addr, 1)) == CONST_INT)
> +    {
> +      unsigned int tmp = 1 << (ffs_hwi (INTVAL (XEXP (addr, 1))) - 1);
> +      /* ALIGN is in bits.  */
> +      tmp <<= 3;
> +      align = REGNO_POINTER_ALIGN (REGNO (XEXP (addr, 0)));
> +      align = (align > tmp) ? tmp : align;
> +    }
> +
> +  if (align > mode_mem_attrs[(int) mode]->align)
> +    set_mem_align (rt, align);
> +
>    return rt;
>  }
> 
>