public inbox for gcc-bugs@sourceware.org
help / color / mirror / Atom feed
* [Bug libgcc/94220] New: libgcc FTB for ARM Thump when optimizing for size
@ 2020-03-19  0:56 npl at chello dot at
  2020-03-23 11:29 ` [Bug target/94220] libgcc FTB for ARM Thumb " rearnsha at gcc dot gnu.org
                   ` (4 more replies)
  0 siblings, 5 replies; 6+ messages in thread
From: npl at chello dot at @ 2020-03-19  0:56 UTC (permalink / raw)
  To: gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94220

            Bug ID: 94220
           Summary: libgcc FTB for ARM Thump when optimizing for size
           Product: gcc
           Version: 10.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: libgcc
          Assignee: unassigned at gcc dot gnu.org
          Reporter: npl at chello dot at
                CC: rearnsha at arm dot com
  Target Milestone: ---

This issue was introduced with 6b9ce2b4eb49e3c930730c3721323349e2136b1a,
the sections guarded with __OPTIMIZE_SIZE__ where apparently left out

/tmp/b/.build/arm-none-eabi/src/gcc/libgcc/config/arm/lib1funcs.S:1139: Error:
cannot honor width suffix -- `mul r2,r0'
/tmp/b/.build/arm-none-eabi/src/gcc/libgcc/config/arm/lib1funcs.S:1140: Error:
cannot honor width suffix -- `sub r1,r1,r2'
/tmp/b/.build/arm-none-eabi/src/gcc/libgcc/config/arm/lib1funcs.S:1238: Error:
MOV Rd, Rs with two low registers is not permitted on this architecture -- `mov
work,dividend'
/tmp/b/.build/arm-none-eabi/src/gcc/libgcc/config/arm/lib1funcs.S:1239: Error:
cannot honor width suffix -- `eor work,divisor'
/tmp/b/.build/arm-none-eabi/src/gcc/libgcc/config/arm/lib1funcs.S:1241: Error:
cannot honor width suffix -- `mov curbit,#1'
/tmp/b/.build/arm-none-eabi/src/gcc/libgcc/config/arm/lib1funcs.S:1242: Error:
cannot honor width suffix -- `mov result,#0'
/tmp/b/.build/arm-none-eabi/src/gcc/libgcc/config/arm/lib1funcs.S:1245: Error:
cannot honor width suffix -- `neg divisor,divisor'
/tmp/b/.build/arm-none-eabi/src/gcc/libgcc/config/arm/lib1funcs.S:1249: Error:
cannot honor width suffix -- `neg dividend,dividend'
/tmp/b/.build/arm-none-eabi/src/gcc/libgcc/config/arm/lib1funcs.S:1256: Error:
MOV Rd, Rs with two low registers is not permitted on this architecture -- `mov
r0,result'
/tmp/b/.build/arm-none-eabi/src/gcc/libgcc/config/arm/lib1funcs.S:1260: Error:
cannot honor width suffix -- `neg r0,r0'
/tmp/b/.build/arm-none-eabi/src/gcc/libgcc/config/arm/lib1funcs.S:1351: Error:
cannot honor width suffix -- `mul r2,r0'
/tmp/b/.build/arm-none-eabi/src/gcc/libgcc/config/arm/lib1funcs.S:1352: Error:
cannot honor width suffix -- `sub r1,r1,r2'

(Fix is rather straightforward: add an 's' to every op)

^ permalink raw reply	[flat|nested] 6+ messages in thread

* [Bug target/94220] libgcc FTB for ARM Thumb when optimizing for size
  2020-03-19  0:56 [Bug libgcc/94220] New: libgcc FTB for ARM Thump when optimizing for size npl at chello dot at
@ 2020-03-23 11:29 ` rearnsha at gcc dot gnu.org
  2020-03-26 11:00 ` cvs-commit at gcc dot gnu.org
                   ` (3 subsequent siblings)
  4 siblings, 0 replies; 6+ messages in thread
From: rearnsha at gcc dot gnu.org @ 2020-03-23 11:29 UTC (permalink / raw)
  To: gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94220

Richard Earnshaw <rearnsha at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
            Summary|libgcc FTB for ARM Thump    |libgcc FTB for ARM Thumb
                   |when optimizing for size    |when optimizing for size
           Assignee|unassigned at gcc dot gnu.org      |rearnsha at gcc dot gnu.org

--- Comment #1 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
Mine

^ permalink raw reply	[flat|nested] 6+ messages in thread

* [Bug target/94220] libgcc FTB for ARM Thumb when optimizing for size
  2020-03-19  0:56 [Bug libgcc/94220] New: libgcc FTB for ARM Thump when optimizing for size npl at chello dot at
  2020-03-23 11:29 ` [Bug target/94220] libgcc FTB for ARM Thumb " rearnsha at gcc dot gnu.org
@ 2020-03-26 11:00 ` cvs-commit at gcc dot gnu.org
  2020-03-26 11:02 ` rearnsha at gcc dot gnu.org
                   ` (2 subsequent siblings)
  4 siblings, 0 replies; 6+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2020-03-26 11:00 UTC (permalink / raw)
  To: gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94220

--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Richard Earnshaw <rearnsha@gcc.gnu.org>:

https://gcc.gnu.org/g:e519d644999d04e0a341cb034f4d954963b1d2d2

commit r10-7399-ge519d644999d04e0a341cb034f4d954963b1d2d2
Author: Richard Earnshaw <rearnsha@arm.com>
Date:   Tue Mar 24 14:45:50 2020 +0000

    arm: unified syntax for libgcc when built with -Os [PR94220]

    The recent patch to convert all thumb1 code in libgcc to unified syntax
    ommitted the conditional code that is used only when building the library
    for minimal size.  This patch fixes this case.

    I've also fixed the COND macro so that a single definition is always used
    that is for unified syntax.  This eliminates a warning that is now being
    seen from the assembler when compiling the ieee fp support code.

            PR target/94220
            * config/arm/lib1funcs.asm (COND): Use a single definition for
            unified syntax.
            (aeabi_uidivmod): Unified syntax when optimizing Thumb for size.
            (aeabi_idivmod): Likewise.
            (divsi3_skip_div0_test): Likewise.

^ permalink raw reply	[flat|nested] 6+ messages in thread

* [Bug target/94220] libgcc FTB for ARM Thumb when optimizing for size
  2020-03-19  0:56 [Bug libgcc/94220] New: libgcc FTB for ARM Thump when optimizing for size npl at chello dot at
  2020-03-23 11:29 ` [Bug target/94220] libgcc FTB for ARM Thumb " rearnsha at gcc dot gnu.org
  2020-03-26 11:00 ` cvs-commit at gcc dot gnu.org
@ 2020-03-26 11:02 ` rearnsha at gcc dot gnu.org
  2020-03-27 10:24 ` cvs-commit at gcc dot gnu.org
  2020-03-27 10:26 ` cvs-commit at gcc dot gnu.org
  4 siblings, 0 replies; 6+ messages in thread
From: rearnsha at gcc dot gnu.org @ 2020-03-26 11:02 UTC (permalink / raw)
  To: gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94220

Richard Earnshaw <rearnsha at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |RESOLVED
         Resolution|---                         |FIXED

--- Comment #3 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
Fixed

^ permalink raw reply	[flat|nested] 6+ messages in thread

* [Bug target/94220] libgcc FTB for ARM Thumb when optimizing for size
  2020-03-19  0:56 [Bug libgcc/94220] New: libgcc FTB for ARM Thump when optimizing for size npl at chello dot at
                   ` (2 preceding siblings ...)
  2020-03-26 11:02 ` rearnsha at gcc dot gnu.org
@ 2020-03-27 10:24 ` cvs-commit at gcc dot gnu.org
  2020-03-27 10:26 ` cvs-commit at gcc dot gnu.org
  4 siblings, 0 replies; 6+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2020-03-27 10:24 UTC (permalink / raw)
  To: gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94220

--- Comment #4 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Richard Earnshaw <rearnsha@gcc.gnu.org>:

https://gcc.gnu.org/g:a9cd2d786ad4c45b9349e7fe22131782828d4cbd

commit r10-7413-ga9cd2d786ad4c45b9349e7fe22131782828d4cbd
Author: Richard Earnshaw <rearnsha@arm.com>
Date:   Fri Mar 27 10:23:38 2020 +0000

    fixup: move ChangeLog entry for last Arm fix to correct file.

    PR target/94220

^ permalink raw reply	[flat|nested] 6+ messages in thread

* [Bug target/94220] libgcc FTB for ARM Thumb when optimizing for size
  2020-03-19  0:56 [Bug libgcc/94220] New: libgcc FTB for ARM Thump when optimizing for size npl at chello dot at
                   ` (3 preceding siblings ...)
  2020-03-27 10:24 ` cvs-commit at gcc dot gnu.org
@ 2020-03-27 10:26 ` cvs-commit at gcc dot gnu.org
  4 siblings, 0 replies; 6+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2020-03-27 10:26 UTC (permalink / raw)
  To: gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94220

--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Richard Earnshaw <rearnsha@gcc.gnu.org>:

https://gcc.gnu.org/g:66e0e23c12d143c8caf787d95ff356f009b1fca9

commit r10-7414-g66e0e23c12d143c8caf787d95ff356f009b1fca9
Author: Richard Earnshaw <rearnsha@arm.com>
Date:   Fri Mar 27 10:25:51 2020 +0000

    fixup: move ChangeLog entry for last Arm fix to correct file.

    PR target/94220

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2020-03-27 10:26 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-03-19  0:56 [Bug libgcc/94220] New: libgcc FTB for ARM Thump when optimizing for size npl at chello dot at
2020-03-23 11:29 ` [Bug target/94220] libgcc FTB for ARM Thumb " rearnsha at gcc dot gnu.org
2020-03-26 11:00 ` cvs-commit at gcc dot gnu.org
2020-03-26 11:02 ` rearnsha at gcc dot gnu.org
2020-03-27 10:24 ` cvs-commit at gcc dot gnu.org
2020-03-27 10:26 ` cvs-commit at gcc dot gnu.org

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).