[Bug tree-optimization/94790] New: Failure to use andn in specific pattern in which it is available

[Bug tree-optimization/94790] New: Failure to use andn in specific pattern in which it is available

[gabravier at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94790

            Bug ID: 94790
           Summary: Failure to use andn in specific pattern in which it is
                    available
           Product: gcc
           Version: 10.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: tree-optimization
          Assignee: unassigned at gcc dot gnu.org
          Reporter: gabravier at gmail dot com
  Target Milestone: ---

unsigned r1(unsigned a, unsigned b, unsigned mask)
{
    return a ^ ((a ^ b) & mask);
}

unsigned r2(unsigned a, unsigned b, unsigned mask)
{
    return (~mask & a) | (b & mask);
}

`r1` and `r2` are equivalent. `r2` is translated into `r1` by GCC. LLVM instead
transforms `r1` into `r2` when an "and not" instruction is available. I haven't
benchmarked the resulting code a lot, but basic measurements and llvm-mca
indicates that code using andn is faster than the code using the `r1` pattern
(and the code using andn takes 1 less instruction on x86)

Comparison of generated code with `-mbmi` : https://godbolt.org/z/2PUhBX

[Bug rtl-optimization/94790] Failure to use andn in specific pattern in which it is available

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94790

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Last reconfirmed|                            |2020-04-27
             Status|UNCONFIRMED                 |NEW
          Component|tree-optimization           |rtl-optimization
     Ever confirmed|0                           |1

--- Comment #1 from Richard Biener <rguenth at gcc dot gnu.org> ---
The r2 form should be faster because the dependence chain is one instruction
shorter.  On GIMPLE the first form is cheaper because it's one instruction
less since we do not model a ANDN instruction on GIMPLE.  The andn form
might need one more register though (dependent on surrounding code).

Confirmed.

Either RTL expansion or combine/fwprop would need to recognize the
opportunity.

A PRE-RTL GIMPLE "logical reassoc + insn selection" pass might be another
option.  The final reassoc pass could for example do this.

[Bug rtl-optimization/94790] Failure to use andn in specific pattern in which it is available

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94790

--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
*** Bug 95922 has been marked as a duplicate of this bug. ***

[Bug rtl-optimization/94790] Failure to use andn in specific pattern in which it is available

[luoxhu at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94790

luoxhu at gcc dot gnu.org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |luoxhu at gcc dot gnu.org

--- Comment #3 from luoxhu at gcc dot gnu.org ---
On Power, '(~mask & a) | (b & mask)' is better than 'a ^ ((a ^ b) & mask)' as
the first can be generated as one instruction 'xxsel' as PR90323 shows.

[Bug rtl-optimization/94790] Failure to use andn in specific pattern in which it is available

[luoxhu at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94790

--- Comment #4 from luoxhu at gcc dot gnu.org ---
Just noticed they are different case, scalar vs. vector...

[Bug rtl-optimization/94790] Failure to use andn in specific pattern in which it is available

[crazylht at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94790

Hongtao.liu <crazylht at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |crazylht at gmail dot com

--- Comment #5 from Hongtao.liu <crazylht at gmail dot com> ---
the extra move instrcution can be handle by RAT, but from the perspective of
the pipeline, `andn + and + ior` version take 2 cycles(and and andn doesn't
have dependence), but xor + and + xor will take 3 cycles.

[Bug rtl-optimization/94790] Failure to use andn in specific pattern in which it is available

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94790

--- Comment #6 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by hongtao Liu <liuhongt@gcc.gnu.org>:

https://gcc.gnu.org/g:5f19303ada7db92c155332e7ba317233ca05946b

commit r12-6538-g5f19303ada7db92c155332e7ba317233ca05946b
Author: Haochen Jiang <haochen.jiang@intel.com>
Date:   Wed Jan 12 10:01:21 2022 +0800

    Optimize a ^ ((a ^ b) & mask) to (~mask & a) | (b & mask).

    From the perspective of the pipeline, `andn + and + ior` version take
    2 cycles(AND and ANDN doesn't have dependence), but xor + and + xor
    will take 3 cycles.

    -       xorl    %edi, %esi
            andl    %edx, %esi
    -       movl    %esi, %eax
    -       xorl    %edi, %eax
    +       andn    %edi, %edx, %eax
    +       orl     %esi, %eax

    gcc/ChangeLog:

            PR target/94790
            * config/i386/i386.md (*xor2andn): New define_insn_and_split.

    gcc/testsuite/ChangeLog:

            PR target/94790
            * gcc.target/i386/pr94790-1.c: New test.
            * gcc.target/i386/pr94790-2.c: Ditto.

[Bug rtl-optimization/94790] Failure to use andn in specific pattern in which it is available

[crazylht at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94790

--- Comment #7 from Hongtao.liu <crazylht at gmail dot com> ---
Fixed in GCC12 for x86.

[Bug rtl-optimization/94790] Failure to use andn in specific pattern in which it is available

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94790

--- Comment #8 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by hongtao Liu <liuhongt@gcc.gnu.org>:

https://gcc.gnu.org/g:b77e3b4e4589e56c01511fabdbaadb029cd47f5c

commit r12-6567-gb77e3b4e4589e56c01511fabdbaadb029cd47f5c
Author: liuhongt <hongtao.liu@intel.com>
Date:   Thu Jan 13 22:51:49 2022 +0800

    Fix ICE of unrecognizable insn. [PR target/104001]

    For define_insn_and_split "*xor2andn":

    1. Refine predicate of operands[0] from nonimmediate_operand to
    register_operand.
    2. Remove TARGET_AVX512BW from condition to avoid kmov when TARGET_BMI
    is not available.

    gcc/ChangeLog:

            PR target/104001
            PR target/94790
            PR target/104014
            * config/i386/i386.md (*xor2andn): Refine predicate of
            operands[0] from nonimmediate_operand to
            register_operand, remove TARGET_AVX512BW from condition.

    gcc/testsuite/ChangeLog:

            * gcc.target/i386/pr104001.c: New test.