[Bug tree-optimization/96172] New: Failure to optimize direct assignment to bitfield through shifts

[Bug tree-optimization/96172] New: Failure to optimize direct assignment to bitfield through shifts

[gabravier at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96172

            Bug ID: 96172
           Summary: Failure to optimize direct assignment to bitfield
                    through shifts
           Product: gcc
           Version: 11.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: tree-optimization
          Assignee: unassigned at gcc dot gnu.org
          Reporter: gabravier at gmail dot com
  Target Milestone: ---

struct ret_struct
{
    union
    {
        struct
        {
            unsigned int a : 1;
            unsigned int b : 1;
            unsigned int c : 1;
        };
        unsigned char as_char;
    };
};

ret_struct f1(uint32_t x)
{
    x >>= 16;
    ret_struct result;
    result.a = x;
    result.b = (x >> 1);
    result.c = (x >> 2);
    return result;
}
// Compiling f1 with GCC yields code equivalent to f2
ret_struct f2(uint32_t x)
{
    uint32_t a = (x >> 17) & 1;
    uint32_t d = x;
    a += a;
    x = ((x >> 18) & 1) << 2;

    ret_struct result;
    result.as_char = ((a | ((d >> 16) & 1)) | x);
    return result;
}
// Compiling f2 with GCC yields code equivalent to f3
ret_struct f3(uint32_t x)
{
    x >>= 16;
    ret_struct result;
    result.as_char = (x & 1) | ((x & 2) | (x & 4));
    return result;
}
// Compiling f3 with GCC yields code equivalent to f4
ret_struct f4(uint32_t x)
{
    ret_struct result;
    result.as_char = (x >> 16) & 7;
    return result;
}

f1 and f2 can be directly optimized to f4. That transformation is done by LLVM,
but not by GCC.

Additionally, even directly compiling f4 with GCC doesn't yield an optimal code
generation on architectures like x86. GCC generates this :

f4(unsigned int):
  shr edi, 16
  and edi, 7
  xor eax, eax
  mov al, dil
  ret

and LLVM generates this :

f4(unsigned int):
  mov eax, edi
  shr eax, 16
  and eax, 7
  ret

[Bug tree-optimization/96172] Failure to optimize direct assignment to bitfield through shifts

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96172

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Severity|normal                      |enhancement

[Bug tree-optimization/96172] Failure to optimize direct assignment to bitfield through shifts

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96172

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
     Ever confirmed|0                           |1
   Last reconfirmed|                            |2022-12-15
             Status|UNCONFIRMED                 |ASSIGNED
           Assignee|unassigned at gcc dot gnu.org      |pinskia at gcc dot gnu.org

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
I think I have patches for this but won't get to it until next year.

[Bug tree-optimization/96172] Failure to optimize direct assignment to bitfield through shifts

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96172

--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Note for aarch64 GCC produces decent code already (since GCC 9):
f1(unsigned int):
.LFB0:
        .cfi_startproc
        ubfx    x0, x0, 16, 3
        ret

But the gimple level is missed ...