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* [Bug other/97585] New: Improve documentation for -march=x86-64 to say MMX, SSE, SSE2 are implied
@ 2020-10-27 0:26 max at quendi dot de
2023-07-10 5:14 ` [Bug target/97585] " pinskia at gcc dot gnu.org
2023-07-10 6:29 ` crazylht at gmail dot com
0 siblings, 2 replies; 3+ messages in thread
From: max at quendi dot de @ 2020-10-27 0:26 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97585
Bug ID: 97585
Summary: Improve documentation for -march=x86-64 to say MMX,
SSE, SSE2 are implied
Product: gcc
Version: 10.2.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: other
Assignee: unassigned at gcc dot gnu.org
Reporter: max at quendi dot de
Target Milestone: ---
The documentation at https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html is
pretty good when it comes to indicating which instruction set extensions are
supported by which `march` value.
But -march=x86-64 is an exception: It just states "A generic CPU with 64-bit
extensions." but does not make it clear that this implies MMX, SSE, SSE2
(according to the content of gcc/common/config/i386/i386-common.c). This is
only mentioned (as far as I could tell) in one place, indirectly, in the
documentation for -mfpmath where it says:
> For the x86-32 compiler, you must use -march=cpu-type, -msse or -msse2 switches to enable SSE extensions and make this option effective. For the x86-64 compiler, these extensions are enabled by default.
I suggest to change
> A generic CPU with 64-bit extensions.
to something like this, matching the phrasing of other architectures like
pentium4, nocona etc.:
> A generic CPU with 64-bit extensions, MMX, SSE and SSE2 instruction set support.
^ permalink raw reply [flat|nested] 3+ messages in thread
* [Bug target/97585] Improve documentation for -march=x86-64 to say MMX, SSE, SSE2 are implied
2020-10-27 0:26 [Bug other/97585] New: Improve documentation for -march=x86-64 to say MMX, SSE, SSE2 are implied max at quendi dot de
@ 2023-07-10 5:14 ` pinskia at gcc dot gnu.org
2023-07-10 6:29 ` crazylht at gmail dot com
1 sibling, 0 replies; 3+ messages in thread
From: pinskia at gcc dot gnu.org @ 2023-07-10 5:14 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97585
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Severity|normal |enhancement
Ever confirmed|0 |1
Status|UNCONFIRMED |NEW
Last reconfirmed| |2023-07-10
--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Confirmed.
^ permalink raw reply [flat|nested] 3+ messages in thread
* [Bug target/97585] Improve documentation for -march=x86-64 to say MMX, SSE, SSE2 are implied
2020-10-27 0:26 [Bug other/97585] New: Improve documentation for -march=x86-64 to say MMX, SSE, SSE2 are implied max at quendi dot de
2023-07-10 5:14 ` [Bug target/97585] " pinskia at gcc dot gnu.org
@ 2023-07-10 6:29 ` crazylht at gmail dot com
1 sibling, 0 replies; 3+ messages in thread
From: crazylht at gmail dot com @ 2023-07-10 6:29 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97585
Hongtao.liu <crazylht at gmail dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |crazylht at gmail dot com
--- Comment #2 from Hongtao.liu <crazylht at gmail dot com> ---
It's now documented in x86psABI
Table 3.1: Micro-Architecture Levels
Level Name CPU Feature Example instruction
(baseline)
CMOV cmov
CX8 cmpxchg8b
FPU fld
FXSR fxsave
MMX emms
OSFXSR fxsave
SCE syscall
SSE cvtss2si
SSE2 cvtpi2pd
x86-64-v2
CMPXCHG16B cmpxchg16b
LAHF-SAHF lahf
POPCNT popcnt
SSE3 addsubpd
SSE4_1 blendpd
SSE4_2 pcmpestri
SSSE3 phaddd
x86-64-v3
AVX vzeroall
AVX2 vpermd
BMI1 andn
BMI2 bzhi
F16C vcvtph2ps
FMA vfmadd132pd
LZCNT lzcnt
MOVBE movbe
OSXSAVE xgetbv
x86-64-v4 AVX512F kmovw
AVX512BW vdbpsadbw
AVX512CD vplzcntd
AVX512DQ vpmullq
AVX512VL n/a
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2023-07-10 6:29 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2020-10-27 0:26 [Bug other/97585] New: Improve documentation for -march=x86-64 to say MMX, SSE, SSE2 are implied max at quendi dot de
2023-07-10 5:14 ` [Bug target/97585] " pinskia at gcc dot gnu.org
2023-07-10 6:29 ` crazylht at gmail dot com
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