[Bug target/99321] [11 Regression] ICE: in extract_constrain_insn, at recog.c:2670: insn does not satisfy its constraints: {*uminv16qi3} since r11-7121-g37876976b0511ec9

["jakub at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99321

--- Comment #2 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
I'm afraid we have multiple problems with -mavx512vl -mno-avx512bw (are there
any CPUs with that combination of ISA sets though?).
In r7-618-g9bdf001b7a2232753e4a92582218bb4f24c8d809 I've fixed the 16-byte
vp{min,max}ub to not allow v constraints when not AVX512BW.
But clearly many other patterns need something like that and don't have that.
E.g. vp{add,sub,{min,max},{u,s}}{b,w}, both 16-byte and 32-byte.
The result of that aren't ICEs, but code silently using AVX512BW features when
AVX512VL is enabled but AVX512BW is not.
Similarly, vpmullq needs AVX512DQ.

And, another thing is that the:
(define_peephole2
  [(set (match_operand 0 "sse_reg_operand")
        (match_operand 1 "sse_reg_operand"))
   (set (match_dup 0)
        (match_operator 3 "commutative_operator"
          [(match_dup 0)
           (match_operand 2 "memory_operand")]))]
  "REGNO (operands[0]) != REGNO (operands[1])"
  [(set (match_dup 0) (match_dup 2))
   (set (match_dup 0)
        (match_op_dup 3 [(match_dup 0) (match_dup 1)]))])
peephole2 doesn't work and results in ICEs if the patterns are correct (as is
the case of *uminv16qi3) if one is unlucky and operands[1] is [xy]mm16 or
higher register and operands[0] is not.