[Bug target/99321] [11 Regression] ICE: in extract_constrain_insn, at recog.c:2670: insn does not satisfy its constraints: {*uminv16qi3} since r11-7121-g37876976b0511ec9

["cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99321

--- Comment #4 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jakub Jelinek <jakub@gcc.gnu.org>:

https://gcc.gnu.org/g:f1b13064609a41fcaf4d1859663453bba237e277

commit r11-7474-gf1b13064609a41fcaf4d1859663453bba237e277
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Wed Mar 3 10:06:14 2021 +0100

    i386: Fix a peephole2 for -mavx512vl -mno-avx512bw [PR99321]

    As the testcase shows, the
    (define_peephole2
      [(set (match_operand 0 "sse_reg_operand")
            (match_operand 1 "sse_reg_operand"))
       (set (match_dup 0)
            (match_operator 3 "commutative_operator"
              [(match_dup 0)
               (match_operand 2 "memory_operand")]))]
    peephole2 can for AVX512VL without AVX512BW (I guess it is a hyphothetical
    CPU, but unfortunately they are separate CPUID bits and we have separate
    options for them) turn something that is valid without that peephole2
    into something that is invalid (and in this case ICEs).
    The problem is that the vpadd[bw], vpmullw, vpmin[su][bw] and vpmax[su][bw]
    instructions require both AVX512BW and AVX512VL when they have
    16-byte or 32-byte operands.  If operands[0] is %[xy]mm0 .. %[xy]mm15
    but operands[1] is %[xy]mm16 .. %[xy]mm31, then before we have
    a vector move which uses vmovdqa{32,64} and doesn't need AVX512BW,
    AVX512VL is I think implied from HARD_REGNO_MODE_OK only supporting
    V{16Q,32Q,8H,16H}imode in EXT_REX_SSE_REGNO_P regs with AVX512VL, and then
    we have a commutative operation with that %[xy]mm0 .. %[xy]mm15 destination
    and one source and a memory operand, so VEX encoded operation.
    And, the peephole2 wants to replace it with a load into the destination
    register from memory (ok) and then the commutative arith instruction.
    But that needs EVEX encoding because of the high register and so requires
    AVX512BW which might not be enabled.
    The exception is and/ior/xor, because the hw doesn't have
    vp{and,or,xor}{b,w} instructions at all, it uses vp{and,or,xor}d instead
    and that of course doesn't need AVX512BW.

    BTW, there are other bugs I need to look at, while the vp{min,max}ub with
    16-byte operands instruction properly requires avx512bw for v constraints
    and otherwise uses x, e.g. the vpadd[bw] etc. instructions don't.
    I'll try to handle that incrementally later this week.

    2021-03-03  Jakub Jelinek  <jakub@redhat.com>

            PR target/99321
            * config/i386/predicates.md (logic_operator): New define_predicate.
            * config/i386/i386.md (mov + mem using comm arith peephole2):
            Punt if operands[1] is EXT_REX_SSE_REGNO_P, AVX512BW is not enabled
            and the inner mode is [QH]Imode.

            * gcc.target/i386/pr99321.c: New test.