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From: "gjl at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/99435] avr: incorrect I/O address ranges for some cores
Date: Wed, 26 Oct 2022 21:21:12 +0000	[thread overview]
Message-ID: <bug-99435-4-g2Fa06IPNi@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-99435-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99435

--- Comment #1 from Georg-Johann Lay <gjl at gcc dot gnu.org> ---
I am really confused.

To all of my knowledge, IN and OUT can address a range of 64 bytes.  For
example, the opcode of OUT is

1011 1AAr rrrr AAAA

where "r" bits encode for the register number (2^5 = 32 of them) and "A" bits
encode absolute target addresses (2^6 = 64 of them). So there isn't even enough
space in the instruction encoding to provide an address range as clained by
this PR.

Similar for, say, SBI with opcode encoding

1011 1010 AAAA Abbb

where "A" bits encode for absolute target address (2^5 = 32 of them) and "b"
encode target bit number (2^3 = 8 of them).

Are you sure you didn't just stumble upon a typo in the data sheet?

All AVRs are using these encodings.  The only difference is between Xmega and
non-Xmega which use different, implicit SFR_OFFSETs (which don't affect the
encoding or the number of address that can be encoded).

  reply	other threads:[~2022-10-26 21:21 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-06 20:15 [Bug target/99435] New: " gcc at nothien dot uber.space
2022-10-26 21:21 ` gjl at gcc dot gnu.org [this message]
2023-01-25 18:28 ` [Bug target/99435] " gjl at gcc dot gnu.org
2023-05-28 10:49 ` gjl at gcc dot gnu.org

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