[Bug target/99435] avr: incorrect I/O address ranges for some cores

["gjl at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99435

Georg-Johann Lay <gjl at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|WAITING                     |RESOLVED
         Resolution|---                         |INVALID

--- Comment #3 from Georg-Johann Lay <gjl at gcc dot gnu.org> ---
Closed as invalid.

The linked ATmega16U4 states on page 26:

> 5. AVR Memories
> 5.4 I/O Memory
> [...]
> I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible
> using the SBI and CBI instructions. In these registers, the value of single
> bits can be checked by using the SBIS and SBIC instructions. Refer to the
> instruction set section for more details. When using the I/O specific commands
> IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
> Registers as data space using LD and ST instructions, 0x20 must be added to
> these addresses. The device is a complex microcontroller with more peripheral
> units than can be supported within the 64 location reserved in Opcode for the
> IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM,
> only the ST/STS/STD and LD/LDS/LDD instructions can be used.

So the lower I/O has a range of 5 bits (CBI, SBI, SBIC, SBIS), and the I/O
addressable by IN and OUT has a range of 6 bits.