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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/99822] [11 Regression] Assembler messages: Error: integer register expected in the extended/shifted operand register at operand 3 -- `adds x1,xzr,#2' Date: Tue, 30 Mar 2021 14:44:32 +0000 [thread overview] Message-ID: <bug-99822-4-9Szag5hBtW@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-99822-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99822 --- Comment #3 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Kyrylo Tkachov <ktkachov@gcc.gnu.org>: https://gcc.gnu.org/g:19199a6f2b0f4ce4b100856c78706d56a16b1956 commit r11-7912-g19199a6f2b0f4ce4b100856c78706d56a16b1956 Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com> Date: Tue Mar 30 15:43:36 2021 +0100 aarch64: PR target/99822 Don't allow zero register in first operand of SUBS/ADDS-immediate In this PR we end up generating an invalid instruction: adds x1,xzr,#2 because the pattern accepts zero as an operand in the comparison, but the instruction doesn't. Fix it by adjusting the predicate and constraints. gcc/ChangeLog: PR target/99822 * config/aarch64/aarch64.md (sub<mode>3_compare1_imm): Do not allow zero in operand 1. gcc/testsuite/ChangeLog: PR target/99822 * gcc.c-torture/compile/pr99822.c: New test.
next prev parent reply other threads:[~2021-03-30 14:44 UTC|newest] Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-03-30 4:25 [Bug target/99822] New: " asolokha at gmx dot com 2021-03-30 7:48 ` [Bug target/99822] [11 Regression] " ktkachov at gcc dot gnu.org 2021-03-30 8:09 ` ktkachov at gcc dot gnu.org 2021-03-30 14:44 ` cvs-commit at gcc dot gnu.org [this message] 2021-03-30 14:45 ` ktkachov at gcc dot gnu.org
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