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From: "asolokha at gmx dot com" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/99822] New: Assembler messages: Error: integer register expected in the extended/shifted operand register at operand 3 -- `adds x1,xzr,#2' Date: Tue, 30 Mar 2021 04:25:45 +0000 [thread overview] Message-ID: <bug-99822-4@http.gcc.gnu.org/bugzilla/> (raw) https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99822 Bug ID: 99822 Summary: Assembler messages: Error: integer register expected in the extended/shifted operand register at operand 3 -- `adds x1,xzr,#2' Product: gcc Version: 11.0 Status: UNCONFIRMED Keywords: assemble-failure Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: asolokha at gmx dot com Target Milestone: --- Target: aarch64-linux-gnu GNU as 2.35.2 fails to assemble output of gcc-11.0.1-alpha20210328 snapshot (g:499fa254ae8c9752d8c2cf3130b13ffddfd83546) generated w/ -O1 for the following testcase: int zt, bm, p5 = 1; void __attribute__ ((cold)) l2 (unsigned long int hz) { __int128 d9 = 0; unsigned long int *mg = hz ? &hz : (unsigned long int *) &d9; while (d9 < 1) { bm = bm > d9; bm = bm == (d9 = bm || hz); hz = 0x197000000; d9 = hz * hz; while (p5 < 1) { bm = ((hz = 3) ? zt : 0) > 0x1001; if (bm != 0) { __int128 *nd = (__int128 *) bm; *nd /= 3; } *mg = 0x1001; p5 -= *mg; } for (zt = 0; zt >= 0; zt += 2) d9 = 0; d9 += 2; } } % aarch64-linux-gnu-gcc-11.0.1 -O1 -w -c drr4usrh.c /tmp/ccu8CYtI.s: Assembler messages: /tmp/ccu8CYtI.s:109: Error: integer register expected in the extended/shifted operand register at operand 3 -- `adds x1,xzr,#2'
next reply other threads:[~2021-03-30 4:25 UTC|newest] Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-03-30 4:25 asolokha at gmx dot com [this message] 2021-03-30 7:48 ` [Bug target/99822] [11 Regression] " ktkachov at gcc dot gnu.org 2021-03-30 8:09 ` ktkachov at gcc dot gnu.org 2021-03-30 14:44 ` cvs-commit at gcc dot gnu.org 2021-03-30 14:45 ` ktkachov at gcc dot gnu.org
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