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From: Kyrylo Tkachov <ktkachov@sourceware.org> To: gcc-cvs-wwwdocs@gcc.gnu.org Subject: gcc-wwwdocs branch master updated. a19f3d62fd49243b50346814a0b9dc9f671dac73 Date: Tue, 26 Jan 2021 14:18:28 +0000 (GMT) [thread overview] Message-ID: <20210126141828.7596B3851C01@sourceware.org> (raw) This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "gcc-wwwdocs". The branch, master has been updated via a19f3d62fd49243b50346814a0b9dc9f671dac73 (commit) from f7288746f791239cee98374ac1055f1b9c4d74fa (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit a19f3d62fd49243b50346814a0b9dc9f671dac73 Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com> Date: Mon Jan 25 09:35:35 2021 +0000 arm,aarc64: add initial gcc-11/changes.html entries diff --git a/htdocs/gcc-11/changes.html b/htdocs/gcc-11/changes.html index 13a35e09..9d2e4f29 100644 --- a/htdocs/gcc-11/changes.html +++ b/htdocs/gcc-11/changes.html @@ -361,11 +361,60 @@ a work-in-progress.</p> <!-- .................................................................. --> <h2 id="targets">New Targets and Target Specific Improvements</h2> -<!-- <h3 id="aarch64">AArch64</h3> --> +<h3 id="arm-targets">AArch64 & arm</h3> +<ul> + <li>A number of new CPUs are supported through arguments to the + <code>-mcpu</code> and <code>-mtune</code> options in both + the arm and aarch64 backends (GCC identifiers in parentheses): + <ul> + <li>Arm Cortex-A78 (<code>cortex-a78</code>).</li> + <li>Arm Cortex-A78AE (<code>cortex-a78ae</code>).</li> + <li>Arm Cortex-A78C (<code>cortex-a78c</code>).</li> + <li>Arm Cortex-X1 (<code>cortex-x1</code>).</li> + <li>Arm Neoverse V1 (<code>neoverse-v1</code>).</li> + <li>Arm Neoverse N2 (<code>neoverse-n2</code>).</li> + </ul> + </li> + <li>GCC can now auto-vectorize operations performing + addition, subtraction, multiplication and the accumulate/subtract variants + on complex numbers, taking advantage of the Advanced SIMD instructions in + the Armv8.3-a (AArch64/AArch32), SVE (AArch64), SVE2 (AArch64) and MVE + (AArch32 M-profile) instruction sets.</li> +</ul> + + +<h3 id="aarch64">AArch64</h3> +<ul> + <li> In addition to the above, the following AArch64-only + CPUs are now supported: + <ul> + <li>Fujitsu A64FX (<code>a64fx</code>).</li> + <li>Arm Cortex-R82 (<code>cortex-r82</code>).</li> + </ul> + </li> + <li>The AArch64 Armv8-R architecture is now supported through the + <code>-march=armv8-r</code> option.</li> + <li>Mitigation against the + <a href="https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability/downloads/straight-line-speculation">Straight-line Speculation vulnerability</a> + is supported with the <code>-mharden-sls=</code> option. Please refer to the + documentation for usage instructions.</li> + <li>The availability of Advanced SIMD intrinsics available through the + <code>arm_neon.h</code> header is improved and GCC 11.0 supports the full + set of intrinsics defined by ACLE Q3 2020.</li> +</ul> <!-- <h3 id="arc">ARC</h3> --> -<!-- <h3 id="arm">ARM</h3> --> +<h3 id="arm">arm</h3> +<ul> + <li>Initial auto-vectorization is now available when targeting the MVE + instruction set.</li> + <li>GCC can now make use of the Low Overhead Branch instruction in Armv8.1-M + to optimize loop counters and checks.</li> + <li>The <code>-mcpu=cortex-m55</code> option now supports the extensions + <code>+nomve</code> and <code>+nomve.fp</code> to control generation of + MVE and MVE floating-point instructions.</li> +</ul> <!-- <h3 id="avr">AVR</h3> --> ----------------------------------------------------------------------- Summary of changes: htdocs/gcc-11/changes.html | 53 ++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 51 insertions(+), 2 deletions(-) hooks/post-receive -- gcc-wwwdocs
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