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From: Haochen Jiang <jianghc@sourceware.org> To: gcc-cvs-wwwdocs@gcc.gnu.org Subject: gcc-wwwdocs branch master updated. 4b2333befaeb25f4976c8287e519aba020d61243 Date: Mon, 17 Jul 2023 06:44:17 +0000 (GMT) [thread overview] Message-ID: <20230717064417.55AE63858D1E@sourceware.org> (raw) This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "gcc-wwwdocs". The branch, master has been updated via 4b2333befaeb25f4976c8287e519aba020d61243 (commit) from 67c0749d0cce5a961d19c4a0a80f4750638959fa (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 4b2333befaeb25f4976c8287e519aba020d61243 Author: Haochen Jiang <haochen.jiang@intel.com> Date: Mon Jul 17 11:28:03 2023 +0800 gcc-13/14: Mention Intel new ISA and march support diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html index 39414e18..68e8c5cc 100644 --- a/htdocs/gcc-13/changes.html +++ b/htdocs/gcc-13/changes.html @@ -593,6 +593,10 @@ You may also want to check out our </li> <li>GCC now supports the Intel CPU named Granite Rapids through <code>-march=graniterapids</code>. + The switch enables the AMX-FP16, PREFETCHI ISA extensions. + </li> + <li>GCC now supports the Intel CPU named Granite Rapids D through + <code>-march=graniterapids-d</code>. The switch enables the AMX-FP16, PREFETCHI and AMX-COMPLEX ISA extensions. </li> <li>GCC now supports AMD CPUs based on the <code>znver4</code> core diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html index 3f797642..dad1ba53 100644 --- a/htdocs/gcc-14/changes.html +++ b/htdocs/gcc-14/changes.html @@ -108,7 +108,39 @@ a work-in-progress.</p> <!-- <h3 id="avr">AVR</h3> --> -<!-- <h3 id="x86">IA-32/x86-64</h3> --> +<h3 id="x86">IA-32/x86-64</h3> +<ul> + <li>New ISA extension support for Intel AVX-VNNI-INT16 was added. + AVX-VNNI-INT16 intrinsics are available via the <code>-mavxvnniint16</code> + compiler switch. + </li> + <li>New ISA extension support for Intel SHA512 was added. + SHA512 intrinsics are available via the <code>-msha512</code> + compiler switch. + </li> + <li>New ISA extension support for Intel SM3 was added. + SM3 intrinsics are available via the <code>-msm3</code> + compiler switch. + </li> + <li>New ISA extension support for Intel SM4 was added. + SM4 intrinsics are available via the <code>-msm4</code> + compiler switch. + </li> + <li>GCC now supports the Intel CPU named Arrow Lake through + <code>-march=arrowlake</code>. + Based on Alder Lake, the switch further enables the AVX-IFMA, + AVX-VNNI-INT8, AVX-NE-CONVERT and CMPccXADD ISA extensions. + </li> + <li>GCC now supports the Intel CPU named Arrow Lake S through + <code>-march=arrowlake-s</code>. + Based on Arrow Lake, the switch further enables the AVX-VNNI-INT16, SHA512, + SM3 and SM4 ISA extensions. + </li> + <li>GCC now supports the Intel CPU named Lunar Lake through + <code>-march=lunarlake</code>. + Lunar Lake is based on Arrow Lake S. + </li> +</ul> <!-- <h3 id="mips">MIPS</h3> --> ----------------------------------------------------------------------- Summary of changes: htdocs/gcc-13/changes.html | 4 ++++ htdocs/gcc-14/changes.html | 34 +++++++++++++++++++++++++++++++++- 2 files changed, 37 insertions(+), 1 deletion(-) hooks/post-receive -- gcc-wwwdocs
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