gcc-wwwdocs branch master updated. 9addc5f0c6cea39ff578874cae44b0ffb2b16733

gcc-wwwdocs branch master updated. 9addc5f0c6cea39ff578874cae44b0ffb2b16733

[Gerald Pfeifer]

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- Log -----------------------------------------------------------------
commit 9addc5f0c6cea39ff578874cae44b0ffb2b16733
Author: Gerald Pfeifer <gerald@pfeifer.com>
Date:   Sat Sep 2 14:00:02 2023 +0200

    *: Use "back end" instead of "backend"

diff --git a/htdocs/egcs-1.0/index.html b/htdocs/egcs-1.0/index.html
index 4e674440..34e44931 100644
--- a/htdocs/egcs-1.0/index.html
+++ b/htdocs/egcs-1.0/index.html
@@ -148,7 +148,7 @@ serious problems in EGCS 1.0.1.</p>
     <li> Add missing entries to g77 lang-options.</li>
     <li> Fix problem with -fpedantic in the g77 compiler.</li>
     <li> Fix "backspace" problem with g77 on alphas.</li>
-    <li> Fix x86 backend problem with Fortran literals and -fpic.</li>
+    <li> Fix x86 back end problem with Fortran literals and -fpic.</li>
     <li> Fix some of the problems with negative subscripts for g77 on
          alphas.</li>
     <li> Fixes for Fortran builds on cygwin32/mingw32.</li>
diff --git a/htdocs/egcs-1.1/features.html b/htdocs/egcs-1.1/features.html
index b72445a7..259abd5b 100644
--- a/htdocs/egcs-1.1/features.html
+++ b/htdocs/egcs-1.1/features.html
@@ -63,7 +63,7 @@
 	<li> x86: Alignment of static store data and jump targets is per
 	Intel recommendations now.  Various improvements throughout the
 	x86 port to improve performance on Pentium processors (including
-        improved epilogue sequences for Pentium chips and backend
+        improved epilogue sequences for Pentium chips and back end
         improvements which should help register allocation on all x86
         variants.  Conditional move support has been fixed and enabled for
         PPro processors.
diff --git a/htdocs/egcs-1.1/index.html b/htdocs/egcs-1.1/index.html
index adeffd37..5db4e342 100644
--- a/htdocs/egcs-1.1/index.html
+++ b/htdocs/egcs-1.1/index.html
@@ -92,7 +92,7 @@ EGCS 1.1:</p>
     <li> Fix a few arm code generation bugs.</li>
     <li> Fixincludes will fix additional broken SCO OpenServer header 
          files.</li>
-    <li> Fix a m68k backend bug which caused invalid offsets in reg+d 
+    <li> Fix a m68k back end bug which caused invalid offsets in reg+d 
          addresses.</li>
     <li> Fix problems with 64bit AIX 4.3 support.</li>
     <li> Fix handling of long longs for varargs/stdarg functions on the 
diff --git a/htdocs/gcc-11/changes.html b/htdocs/gcc-11/changes.html
index 44389172..a00637c6 100644
--- a/htdocs/gcc-11/changes.html
+++ b/htdocs/gcc-11/changes.html
@@ -777,7 +777,7 @@ You may also want to check out our
 <ul>
   <li>A number of new CPUs are supported through arguments to the
   <code>-mcpu</code> and <code>-mtune</code> options in both
-  the arm and aarch64 backends (GCC identifiers in parentheses):
+  the arm and aarch64 back ends (GCC identifiers in parentheses):
     <ul>
       <li>Arm Cortex-A78 (<code>cortex-a78</code>).</li>
       <li>Arm Cortex-A78AE (<code>cortex-a78ae</code>).</li>
diff --git a/htdocs/gcc-12/changes.html b/htdocs/gcc-12/changes.html
index b10f2aa4..b4e29d72 100644
--- a/htdocs/gcc-12/changes.html
+++ b/htdocs/gcc-12/changes.html
@@ -755,7 +755,7 @@ function Multiply (S1, S2 : Sign) return Sign is
 <h3 id="bpf">BPF</h3>
 <ul>
   <li>Support for CO-RE (compile-once, run-everywhere) has been added
-      to the BPF backend.  CO-RE allows to compile portable BPF
+      to the BPF back end.  CO-RE allows to compile portable BPF
       programs that are able to run among different versions of the
       Linux kernel.
   </li>
diff --git a/htdocs/gcc-2.95/features.html b/htdocs/gcc-2.95/features.html
index 0e4f6c47..98ca0dd4 100644
--- a/htdocs/gcc-2.95/features.html
+++ b/htdocs/gcc-2.95/features.html
@@ -49,7 +49,7 @@
   </ul></li>
   <li>New Targets and Target Specific Improvements
   <ul>
-    <li><a href="../news/sparc.html">SPARC backend rewrite</a>.</li>
+    <li><a href="../news/sparc.html">SPARC back end rewrite</a>.</li>
     <li>-mschedule=8000 will optimize code for PA8000 class processors;
      -mpa-risc-2-0 will generate code for PA2.0 processors</li>
     <li>Various micro-optimizations for the ia32 port. K6 optimizations</li>
@@ -200,7 +200,7 @@ enabled by default in future releases.  Use the option
     <ul>
 	<li>Work around bug in Sun V5.0 compilers which caused bootstrap
 	    comparison failures on SPARC targets.</li>
-	<li>Fix SPARC backend bug which caused aborts in final.c.</li>
+	<li>Fix SPARC back end bug which caused aborts in final.c.</li>
 	<li>Fix sparc-hal-solaris2* configuration fragments.</li>
 	<li>Fix bug in sparc block profiling.</li>
 	<li>Fix obscure code generation bug for the PARISC targets.</li>
diff --git a/htdocs/gcc-4.9/changes.html b/htdocs/gcc-4.9/changes.html
index 9090c0ea..26d4843a 100644
--- a/htdocs/gcc-4.9/changes.html
+++ b/htdocs/gcc-4.9/changes.html
@@ -498,10 +498,10 @@ auto incr(T x) { return x++; }
        been added. The Advanced SIMD intrinsics have also been improved.
      </li>
      <li> The new local register allocator (LRA) is now on by default
-       for the AArch64 backend.
+       for the AArch64 back end.
      </li>
      <li> The REE (Redundant extension elimination) pass has now been enabled
-       by default for the AArch64 backend.
+       by default for the AArch64 back end.
      </li>
      <li> Tuning for the Cortex-A53 and Cortex-A57 has been improved.
      </li>
@@ -510,7 +510,7 @@ auto incr(T x) { return x++; }
        </code> option.
      </li>
      <li> A number of structural changes have been made to both the ARM
-       and AArch64 backends to facilitate improved code-generation.
+       and AArch64 back ends to facilitate improved code-generation.
      </li>
      <li> As of GCC 4.9.2 a workaround for the ARM Cortex-A53 erratum
        835769 has been added and can be enabled by giving the
@@ -562,7 +562,7 @@ auto incr(T x) { return x++; }
        been added. This is on by default for all targets except VxWorks RTP.
      </li>
      <li> A number of infrastructural changes have been made to both the ARM
-       and AArch64 backends to facilitate improved code-generation.
+       and AArch64 back ends to facilitate improved code-generation.
      </li>
      <li> GCC now supports Cortex-A12 and the Cortex-R7 through the
        <code>-mcpu=cortex-a12</code> and <code>-mcpu=cortex-r7</code> options.
@@ -648,7 +648,8 @@ auto incr(T x) { return x++; }
   </ul>
 <h3 id="msp430">MSP430</h3>
   <ul>
-    <li>A new command-line option <code>-mcpu=</code> has been added to the MSP430 backend.
+    <li>A new command-line option <code>-mcpu=</code> has been added to
+    the MSP430 back end.
     This option is used to specify the ISA to be used.  Accepted values are
     <code>msp430</code> (the default), <code>msp430x</code> and <code>msp430xv2</code>.  The ISA is no longer deduced
     from the <code>-mmcu=</code> option as there are far too many different MCU names.  The
diff --git a/htdocs/gcc-5/changes.html b/htdocs/gcc-5/changes.html
index 6952f866..ab3da60b 100644
--- a/htdocs/gcc-5/changes.html
+++ b/htdocs/gcc-5/changes.html
@@ -675,7 +675,7 @@ here</a>.</p>
       that has support for the Cortex-A72.
      </li>
      <li>The transitional options <code>-mlra</code> and <code>-mno-lra</code>
-       have been removed. The AArch64 backend now uses the local register
+       have been removed. The AArch64 back end now uses the local register
        allocator (LRA) only.
      </li>
    </ul>
@@ -721,7 +721,7 @@ here</a>.</p>
       which are only applicable to the old ABI have been deprecated.
       </li>
       <li>The transitional options <code>-mlra</code> and <code>-mno-lra</code>
-       have been removed. The ARM backend now uses the local register allocator
+       have been removed. The ARM back end now uses the local register allocator
        (LRA) only.
      </li>
      </ul>
diff --git a/htdocs/news.html b/htdocs/news.html
index 2a8b7feb..fb34e64a 100644
--- a/htdocs/news.html
+++ b/htdocs/news.html
@@ -1675,7 +1675,7 @@ changes from the old GCC 2 sources.
 
 <dt><b>September 2, 1999</b></dt>
 <dd>
-Richard Henderson has finished merging the ia32 backend rewrite into the
+Richard Henderson has finished merging the ia32 back end rewrite into the
 mainline GCC sources.  The rewrite is designed to improve optimization
 opportunities for the Pentium II target, but also provides a cleaner
 way to optimize for the Pentium III, AMD-K7 and other high end ia32

-----------------------------------------------------------------------

Summary of changes:
 htdocs/egcs-1.0/index.html    |  2 +-
 htdocs/egcs-1.1/features.html |  2 +-
 htdocs/egcs-1.1/index.html    |  2 +-
 htdocs/gcc-11/changes.html    |  2 +-
 htdocs/gcc-12/changes.html    |  2 +-
 htdocs/gcc-2.95/features.html |  4 ++--
 htdocs/gcc-4.9/changes.html   | 11 ++++++-----
 htdocs/gcc-5/changes.html     |  4 ++--
 htdocs/news.html              |  2 +-
 9 files changed, 16 insertions(+), 15 deletions(-)


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