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From: Haochen Jiang <jianghc@sourceware.org> To: gcc-cvs-wwwdocs@gcc.gnu.org Subject: gcc-wwwdocs branch master updated. 75418ca06871952152d541501e410ce54c08214a Date: Wed, 27 Dec 2023 08:30:18 +0000 (GMT) [thread overview] Message-ID: <20231227083018.5744F3858C62@sourceware.org> (raw) This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "gcc-wwwdocs". The branch, master has been updated via 75418ca06871952152d541501e410ce54c08214a (commit) from 0d8105fd15b33980886283869e980f60f2ca9f04 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 75418ca06871952152d541501e410ce54c08214a Author: Haochen Jiang <haochen.jiang@intel.com> Date: Wed Dec 27 16:30:05 2023 +0800 gcc-13/14: Mention recent update for x86_64 backend Mention AVX10.1 support, APX support and Xeon Phi deprecate in GCC 14. Also adjust documentation in GCC 13. diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html index d3bacc16..b4b1a39a 100644 --- a/htdocs/gcc-13/changes.html +++ b/htdocs/gcc-13/changes.html @@ -543,24 +543,28 @@ You may also want to check out our <code>__bf16</code> type to x86 psABI. Users need to adjust their AVX512BF16-related source code when upgrading GCC12 to GCC13. </li> - <li>New ISA extension support for Intel AVX-IFMA was added. - AVX-IFMA intrinsics are available via the <code>-mavxifma</code> + <li>New ISA extension support for Intel AMX-COMPLEX was added. + AMX-COMPLEX intrinsics are available via the <code>-mamx-complex</code> compiler switch. </li> - <li>New ISA extension support for Intel AVX-VNNI-INT8 was added. - AVX-VNNI-INT8 intrinsics are available via the <code>-mavxvnniint8</code> + <li>New ISA extension support for Intel AMX-FP16 was added. + AMX-FP16 intrinsics are available via the <code>-mamx-fp16</code> + compiler switch. + </li> + <li>New ISA extension support for Intel AVX-IFMA was added. + AVX-IFMA intrinsics are available via the <code>-mavxifma</code> compiler switch. </li> <li>New ISA extension support for Intel AVX-NE-CONVERT was added. AVX-NE-CONVERT intrinsics are available via the <code>-mavxneconvert</code> compiler switch. </li> - <li>New ISA extension support for Intel CMPccXADD was added. - CMPccXADD intrinsics are available via the <code>-mcmpccxadd</code> + <li>New ISA extension support for Intel AVX-VNNI-INT8 was added. + AVX-VNNI-INT8 intrinsics are available via the <code>-mavxvnniint8</code> compiler switch. </li> - <li>New ISA extension support for Intel AMX-FP16 was added. - AMX-FP16 intrinsics are available via the <code>-mamx-fp16</code> + <li>New ISA extension support for Intel CMPccXADD was added. + CMPccXADD intrinsics are available via the <code>-mcmpccxadd</code> compiler switch. </li> <li>New ISA extension support for Intel PREFETCHI was added. @@ -571,10 +575,6 @@ You may also want to check out our RAO-INT intrinsics are available via the <code>-mraoint</code> compiler switch. </li> - <li>New ISA extension support for Intel AMX-COMPLEX was added. - AMX-COMPLEX intrinsics are available via the <code>-mamx-complex</code> - compiler switch. - </li> <li>GCC now supports the Intel CPU named Raptor Lake through <code>-march=raptorlake</code>. Raptor Lake is based on Alder Lake. @@ -585,13 +585,13 @@ You may also want to check out our </li> <li>GCC now supports the Intel CPU named Sierra Forest through <code>-march=sierraforest</code>. - The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD, - ENQCMD and UINTR ISA extensions. + Based on ISA extensions enabled on Alder Lake, the switch further enables + the AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8, CMPccXADD, ENQCMD and UINTR + ISA extensions. </li> <li>GCC now supports the Intel CPU named Grand Ridge through <code>-march=grandridge</code>. - The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD, - ENQCMD, UINTR and RAO-INT ISA extensions. + Grand Ridge is based on Sierra Forest. </li> <li>GCC now supports the Intel CPU named Emerald Rapids through <code>-march=emeraldrapids</code>. @@ -599,11 +599,13 @@ You may also want to check out our </li> <li>GCC now supports the Intel CPU named Granite Rapids through <code>-march=graniterapids</code>. - The switch enables the AMX-FP16 and PREFETCHI ISA extensions. + Based on Sapphire Rapids, the switch further enables the AMX-FP16 and + PREFETCHI ISA extensions. </li> <li>GCC now supports the Intel CPU named Granite Rapids D through <code>-march=graniterapids-d</code>. - The switch enables the AMX-FP16, PREFETCHI and AMX-COMPLEX ISA extensions. + Based on Granite Rapids, the switch further enables the AMX-COMPLEX ISA + extensions. </li> <li>GCC now supports AMD CPUs based on the <code>znver4</code> core via <code>-march=znver4</code>. The switch makes GCC consider diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html index 24e6409a..4b83037a 100644 --- a/htdocs/gcc-14/changes.html +++ b/htdocs/gcc-14/changes.html @@ -320,8 +320,18 @@ a work-in-progress.</p> <h3 id="x86">IA-32/x86-64</h3> <ul> <li>New compiler option <code>-m[no-]evex512</code> was added. - The compiler switch enables/disables 512 bit vector and 64 bit mask - register. It will be default on if AVX512F is enabled. + The compiler switch enables/disables 512-bit vector. + It will be default on if AVX512F is enabled. + </li> + <li>Part of new feature support for Intel APX was added, including EGPR, + NDD, PPX and PUSH2POP2. APX support is available via the + <code>-mapxf</code> compiler switch. + </li> + <li>New ISA extension support for Intel AVX10.1 was added. + AVX10.1 intrinsics are available via the <code>-mavx10.1</code> or + <code>-mavx10.1-256</code> compiler switch with 256-bit vector size + support. 512-bit vector size support for AVX10.1 intrinsics are + available via the <code>-mavx10.1-512</code> compiler switch. </li> <li>New ISA extension support for Intel AVX-VNNI-INT16 was added. AVX-VNNI-INT16 intrinsics are available via the <code>-mavxvnniint16</code> @@ -346,13 +356,12 @@ a work-in-progress.</p> <li>GCC now supports the Intel CPU named Clearwater Forest through <code>-march=clearwaterforest</code>. Based on Sierra Forest, the switch further enables the AVX-VNNI-INT16, - SHA512, SM3, SM4, USER_MSR and PREFETCHI ISA extensions. - extensions. + PREFETCHI, SHA512, SM3, SM4 and USER_MSR ISA extensions. </li> <li>GCC now supports the Intel CPU named Arrow Lake through <code>-march=arrowlake</code>. Based on Alder Lake, the switch further enables the AVX-IFMA, - AVX-VNNI-INT8, AVX-NE-CONVERT and CMPccXADD ISA extensions. + AVX-NE-CONVERT, AVX-VNNI-INT8 and CMPccXADD ISA extensions. </li> <li>GCC now supports the Intel CPU named Arrow Lake S through <code>-march=arrowlake-s</code>. @@ -368,6 +377,14 @@ a work-in-progress.</p> Based on Arrow Lake S, the switch further enables the PREFETCHI ISA extensions. </li> + <li>Xeon Phi CPUs support (a.k.a. Knight Landing and Knight Mill) are marked + as deprecated. GCC will emit a warning when using the + <code>-mavx5124fmaps</code>, <code>-mavx5124vnniw</code>, + <code>-mavx512er</code>, <code>-mavx512pf</code>, + <code>-mprefetchwt1</code>, <code>-march=knl</code>, + <code>-march=knm</code>, <code>-mtune=knl</code> or <code>-mtune=knm</code> + compiler switches. Support will be removed in GCC 15. + </li> </ul> <!-- <h3 id="mcore">MCore</h3> --> ----------------------------------------------------------------------- Summary of changes: htdocs/gcc-13/changes.html | 38 ++++++++++++++++++++------------------ htdocs/gcc-14/changes.html | 27 ++++++++++++++++++++++----- 2 files changed, 42 insertions(+), 23 deletions(-) hooks/post-receive -- gcc-wwwdocs
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