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* [gcc(refs/users/meissner/heads/work046)] Add XXSPLTI32DX support for V4SI/V4SF.
@ 2021-04-12 21:08 Michael Meissner
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From: Michael Meissner @ 2021-04-12 21:08 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:9685d713ac6a6a1aebe3c1db7902215983e09366
commit 9685d713ac6a6a1aebe3c1db7902215983e09366
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Apr 12 17:07:58 2021 -0400
Add XXSPLTI32DX support for V4SI/V4SF.
V4SImode and V4SFmode vectors that are initialized as:
(const_vector [const1, const2, const1, const2])
can be initialized with 2 sets of XXSPLTI32DX instructions.
gcc/
2021-04-12 Michael Meissner <meissner@linux.ibm.com>
* config/rs6000/rs6000.c (xxsplti32dx_constant_p): Add support for
V4SImode and V4SFmode.
* config/rs6000/vsx.md (XXSPLTI32DX): Extend iterator to include
V4SImode and V4SFmode.
(xxsplti32dx_<mode>): Properly handle optimizing the second word
being all 1's.
Diff:
---
gcc/config/rs6000/rs6000.c | 36 ++++++++++++++++++++++++++++++++++++
gcc/config/rs6000/vsx.md | 13 +++++++------
2 files changed, 43 insertions(+), 6 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 7d125d6b65a..db0cbe1edad 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6657,6 +6657,42 @@ xxsplti32dx_constant_p (rtx op,
mode = GET_MODE_INNER (mode);
}
+ else if (mode == V4SImode || mode == V4SFmode)
+ {
+ /* For V4SI/V4SF, the XXSPLTI32DX instruction pair can represent vectors
+ where the two even elements are equal and the two odd elements are
+ equal. */
+ if (GET_CODE (op) != CONST_VECTOR)
+ return false;
+
+ rtx op0 = CONST_VECTOR_ELT (op, 0);
+ if (!rtx_equal_p (op0, CONST_VECTOR_ELT (op, 2)))
+ return false;
+
+ rtx op1 = CONST_VECTOR_ELT (op, 1);
+ if (!rtx_equal_p (op1, CONST_VECTOR_ELT (op, 3)))
+ return false;
+
+ if (TARGET_XXSPLTIW && rtx_equal_p (op0, op1))
+ return false;
+
+ long op0_value;
+ long op1_value;
+ if (mode == V4SImode)
+ {
+ op0_value = INTVAL (op0);
+ op1_value = INTVAL (op1);
+ }
+ else
+ {
+ op0_value = rs6000_const_f32_to_i32 (op0);
+ op1_value = rs6000_const_f32_to_i32 (op1);
+ }
+
+ *constant_ptr = (op0_value << 32) | (op1_value & 0xffffffff);
+ return true;
+ }
+
if (GET_MODE (element) != mode)
return false;
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index ec2c148fb4d..a5bdcc6ead8 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -6348,8 +6348,9 @@
DONE;
})
-;; XXSPLTI32DX used to create 64-bit constants
-(define_mode_iterator XXSPLTI32DX [SF DF V2DF V2DI])
+;; XXSPLTI32DX used to create 64-bit constants or 32-bit vector constants where
+;; the even elements match and the odd elements match.
+(define_mode_iterator XXSPLTI32DX [SF DF V4SF V4SI V2DF V2DI])
(define_insn_and_split "*xxsplti32dx_<mode>"
[(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa")
@@ -6371,11 +6372,11 @@
gcc_unreachable ();
HOST_WIDE_INT high = value >> 32;
- HOST_WIDE_INT low = value & 0xffffffff;
+ HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
- /* If the low bits are 0/-1, initialize that word first. This way we can
- use a smaller XXSPLTIB instruction instead the first XXSPLTI32DX. */
- if (low == 0 || low == -1)
+ /* If the low bits are 0 or all 1s, initialize that word first. This way we
+ can use a smaller XXSPLTIB instruction instead the first XXSPLTI32DX. */
+ if (low == 0 || low == -1)
{
operands[2] = const1_rtx;
operands[3] = GEN_INT (low);
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