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* [gcc(refs/users/meissner/heads/work047)] Revert patches.
@ 2021-04-13 22:01 Michael Meissner
0 siblings, 0 replies; 2+ messages in thread
From: Michael Meissner @ 2021-04-13 22:01 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:d589b1d9c35642e7a15c2c9013fcdaa17a1e4c8b
commit d589b1d9c35642e7a15c2c9013fcdaa17a1e4c8b
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Apr 13 18:00:19 2021 -0400
Revert patches.
gcc/
2021-04-13 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* config/rs6000/altivec.md (UNSPEC_XXBLEND): Move to vsx.md.
(VM3): Move to vsx.md and rename to VBLEND.
(VM3_char): Move to vsx.md and rename to VBLEND_char.
(xxblend_<mode>): Move to vsx.md.
* config/rs6000/vsx.md (UNSPEC_XXEVAL): Move from altivec.md.
(VBLEND): Move from altivec.md and rename VM3 to VBLEND.
(VBLEND_char): Move from altivec.md and rename VM3_char to
VBLEND_char.
(xxblend_<mode>): Move from altivec.md. Use vsx_register_operand
instead of register operand.
gcc/
2021-04-13 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* config/rs6000/altivec.md (UNSPEC_XXEVAL): Move to vsx.md.
(xxeval): Move to vsx.md.
* config/rs6000/vsx.md (UNSPEC_XXEVAL): Move from altivec.md.
(xxeval): Move from altivec.md.
gcc/
2021-04-13 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* config/rs6000/altivec.md (UNSPEC_XXPERMX): Move to vsx.md.
(xxpermx): Move to vsx.md.
(xxpermx_inst): Move to vsx.md.
* config/rs6000/vsx.md (UNSPEC_XXPERMX): Move from altivec.md.
(xxpermx): Move from altivec.md.
(xxpermx_inst): Move from altivec.md.
Diff:
---
gcc/config/rs6000/altivec.md | 86 +++++++++++++++++++++++++++++++++++++++++++
gcc/config/rs6000/vsx.md | 87 --------------------------------------------
2 files changed, 86 insertions(+), 87 deletions(-)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index ed79a6b85cd..9af71e036ab 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -171,10 +171,13 @@
UNSPEC_VPEXTD
UNSPEC_VCLRLB
UNSPEC_VCLRRB
+ UNSPEC_XXEVAL
UNSPEC_VSTRIR
UNSPEC_VSTRIL
UNSPEC_SLDB
UNSPEC_SRDB
+ UNSPEC_XXBLEND
+ UNSPEC_XXPERMX
])
(define_c_enum "unspecv"
@@ -215,6 +218,21 @@
(KF "FLOAT128_VECTOR_P (KFmode)")
(TF "FLOAT128_VECTOR_P (TFmode)")])
+;; Like VM2, just do char, short, int, long, float and double
+(define_mode_iterator VM3 [V4SI
+ V8HI
+ V16QI
+ V4SF
+ V2DF
+ V2DI])
+
+(define_mode_attr VM3_char [(V2DI "d")
+ (V4SI "w")
+ (V8HI "h")
+ (V16QI "b")
+ (V2DF "d")
+ (V4SF "w")])
+
;; Map the Vector convert single precision to double precision for integer
;; versus floating point
(define_mode_attr VS_sxwsp [(V4SI "sxw") (V4SF "sp")])
@@ -799,6 +817,62 @@
"vs<SLDB_lr>dbi %0,%1,%2,%3"
[(set_attr "type" "vecsimple")])
+(define_insn "xxblend_<mode>"
+ [(set (match_operand:VM3 0 "register_operand" "=wa")
+ (unspec:VM3 [(match_operand:VM3 1 "register_operand" "wa")
+ (match_operand:VM3 2 "register_operand" "wa")
+ (match_operand:VM3 3 "register_operand" "wa")]
+ UNSPEC_XXBLEND))]
+ "TARGET_POWER10"
+ "xxblendv<VM3_char> %x0,%x1,%x2,%x3"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
+(define_expand "xxpermx"
+ [(set (match_operand:V2DI 0 "register_operand" "+wa")
+ (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "wa")
+ (match_operand:V2DI 2 "register_operand" "wa")
+ (match_operand:V16QI 3 "register_operand" "wa")
+ (match_operand:QI 4 "u8bit_cint_operand" "n")]
+ UNSPEC_XXPERMX))]
+ "TARGET_POWER10"
+{
+ if (BYTES_BIG_ENDIAN)
+ emit_insn (gen_xxpermx_inst (operands[0], operands[1],
+ operands[2], operands[3],
+ operands[4]));
+ else
+ {
+ /* Reverse value of byte element indexes by XORing with 0xFF.
+ Reverse the 32-byte section identifier match by subracting bits [0:2]
+ of elemet from 7. */
+ int value = INTVAL (operands[4]);
+ rtx vreg = gen_reg_rtx (V16QImode);
+
+ emit_insn (gen_xxspltib_v16qi (vreg, GEN_INT (-1)));
+ emit_insn (gen_xorv16qi3 (operands[3], operands[3], vreg));
+ value = 7 - value;
+ emit_insn (gen_xxpermx_inst (operands[0], operands[2],
+ operands[1], operands[3],
+ GEN_INT (value)));
+ }
+
+ DONE;
+}
+ [(set_attr "type" "vecsimple")])
+
+(define_insn "xxpermx_inst"
+ [(set (match_operand:V2DI 0 "register_operand" "+v")
+ (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "v")
+ (match_operand:V2DI 2 "register_operand" "v")
+ (match_operand:V16QI 3 "register_operand" "v")
+ (match_operand:QI 4 "u3bit_cint_operand" "n")]
+ UNSPEC_XXPERMX))]
+ "TARGET_POWER10"
+ "xxpermx %x0,%x1,%x2,%x3,%4"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
(define_expand "vstrir_<mode>"
[(set (match_operand:VIshort 0 "altivec_register_operand")
(unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand")]
@@ -3436,6 +3510,18 @@
[(set_attr "type" "vecperm")
(set_attr "isa" "p9v,*")])
+(define_insn "xxeval"
+ [(set (match_operand:V2DI 0 "register_operand" "=wa")
+ (unspec:V2DI [(match_operand:V2DI 1 "altivec_register_operand" "wa")
+ (match_operand:V2DI 2 "altivec_register_operand" "wa")
+ (match_operand:V2DI 3 "altivec_register_operand" "wa")
+ (match_operand:QI 4 "u8bit_cint_operand" "n")]
+ UNSPEC_XXEVAL))]
+ "TARGET_POWER10"
+ "xxeval %0,%1,%2,%3,%4"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
(define_expand "vec_unpacku_hi_v16qi"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 5a546146c78..56e3cf6756f 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -271,19 +271,6 @@
;; and Vector Integer Multiply/Divide/Modulo Instructions
(define_mode_iterator VIlong [V2DI V4SI])
-;; Modes for XXBLEND
-(define_mode_iterator VBLEND [V16QI V8HI V4SI V4SF V2DF V2DI])
-
-;; XXBLEND type
-(define_mode_attr VBLEND_char [(V16QI "b")
- (V8HI "h")
- (V4SI "w")
- (V4SF "w")
- (V2DF "d")
- (V2DI "d")])
-
-
-
;; Constants for creating unspecs
(define_c_enum "unspec"
[UNSPEC_VSX_CONCAT
@@ -385,9 +372,6 @@
UNSPEC_XXSPLTIDP
UNSPEC_XXSPLTI32DX
UNSPEC_XXSPLTI32DX_CONST
- UNSPEC_XXPERMX
- UNSPEC_XXEVAL
- UNSPEC_XXBLEND
])
(define_int_iterator XVCVBF16 [UNSPEC_VSX_XVCVSPBF16
@@ -6478,74 +6462,3 @@
"xxsplti32dx %x0,%2,%3"
[(set_attr "type" "vecsimple")
(set_attr "prefixed" "yes")])
-
-;; XXPERMX built-in function support.
-(define_expand "xxpermx"
- [(set (match_operand:V2DI 0 "register_operand" "+wa")
- (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "wa")
- (match_operand:V2DI 2 "register_operand" "wa")
- (match_operand:V16QI 3 "register_operand" "wa")
- (match_operand:QI 4 "u8bit_cint_operand" "n")]
- UNSPEC_XXPERMX))]
- "TARGET_POWER10"
-{
- if (BYTES_BIG_ENDIAN)
- emit_insn (gen_xxpermx_inst (operands[0], operands[1],
- operands[2], operands[3],
- operands[4]));
- else
- {
- /* Reverse value of byte element indexes by XORing with 0xFF.
- Reverse the 32-byte section identifier match by subracting bits [0:2]
- of elemet from 7. */
- int value = INTVAL (operands[4]);
- rtx vreg = gen_reg_rtx (V16QImode);
-
- emit_insn (gen_xxspltib_v16qi (vreg, GEN_INT (-1)));
- emit_insn (gen_xorv16qi3 (operands[3], operands[3], vreg));
- value = 7 - value;
- emit_insn (gen_xxpermx_inst (operands[0], operands[2],
- operands[1], operands[3],
- GEN_INT (value)));
- }
-
- DONE;
-}
- [(set_attr "type" "vecsimple")])
-
-(define_insn "xxpermx_inst"
- [(set (match_operand:V2DI 0 "register_operand" "+v")
- (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "v")
- (match_operand:V2DI 2 "register_operand" "v")
- (match_operand:V16QI 3 "register_operand" "v")
- (match_operand:QI 4 "u3bit_cint_operand" "n")]
- UNSPEC_XXPERMX))]
- "TARGET_POWER10"
- "xxpermx %x0,%x1,%x2,%x3,%4"
- [(set_attr "type" "vecsimple")
- (set_attr "prefixed" "yes")])
-
-;; XXEVAL built-in function support.
-(define_insn "xxeval"
- [(set (match_operand:V2DI 0 "register_operand" "=wa")
- (unspec:V2DI [(match_operand:V2DI 1 "altivec_register_operand" "wa")
- (match_operand:V2DI 2 "altivec_register_operand" "wa")
- (match_operand:V2DI 3 "altivec_register_operand" "wa")
- (match_operand:QI 4 "u8bit_cint_operand" "n")]
- UNSPEC_XXEVAL))]
- "TARGET_POWER10"
- "xxeval %0,%1,%2,%3,%4"
- [(set_attr "type" "vecsimple")
- (set_attr "prefixed" "yes")])
-
-;; XXBLEND built-in function support.
-(define_insn "xxblend_<mode>"
- [(set (match_operand:VBLEND 0 "vsx_register_operand" "=wa")
- (unspec:VBLEND [(match_operand:VBLEND 1 "vsx_register_operand" "wa")
- (match_operand:VBLEND 2 "vsx_register_operand" "wa")
- (match_operand:VBLEND 3 "vsx_register_operand" "wa")]
- UNSPEC_XXBLEND))]
- "TARGET_POWER10"
- "xxblendv<Blenc_char> %x0,%x1,%x2,%x3"
- [(set_attr "type" "vecsimple")
- (set_attr "prefixed" "yes")])
^ permalink raw reply [flat|nested] 2+ messages in thread
* [gcc(refs/users/meissner/heads/work047)] Revert patches.
@ 2021-04-14 18:15 Michael Meissner
0 siblings, 0 replies; 2+ messages in thread
From: Michael Meissner @ 2021-04-14 18:15 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:ac851cd53fd899e8af87cb47c711b071337fd303
commit ac851cd53fd899e8af87cb47c711b071337fd303
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 14 14:14:47 2021 -0400
Revert patches.
gcc/
2021-04-13 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* config/rs6000/rs6000.c (have_compare_and_set_mask): Add IEEE
128-bit floating point types.
* config/rs6000/rs6000.md (FPMASK): New iterator.
(FPMASK2): New iterator.
(Fv mode attribute): Add KFmode and TFmode.
(mov<FPMASK:mode><FPMASK2:mode>cc_fpmask): Replace
mov<SFDF:mode><SFDF2:mode>cc_p9. Add IEEE 128-bit fp support.
(mov<FPMASK:mode><FPMASK2:mode>cc_invert_fpmask): Replace
mov<SFDF:mode><SFDF2:mode>cc_invert_p9. Add IEEE 128-bit fp
support.
(fpmask<mode>): Add IEEE 128-bit fp support. Enable generator to
build te RTL.
(xxsel<mode>): Add IEEE 128-bit fp support. Enable generator to
build te RTL.
gcc/testsuite/
2021-04-13 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* gcc.target/powerpc/float128-cmove.c: New test.
* gcc.target/powerpc/float128-minmax-3.c: New test.
gcc/
2021-04-13 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* config/rs6000/rs6000.c (rs6000_emit_minmax): Add support for ISA
3.1 IEEE 128-bit floating point xsmaxcqp and xsmincqp instructions.
* config/rs6000/rs60000.h (FLOAT128_MIN_MAX_FPMASK_P): New macro.
* config/rs6000/rs6000.md (s<minmax><mode>3): Add support for the
ISA 3.1 IEEE 128-bit minimum and maximum instructions.
gcc/testsuite/
2021-04-13 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* gcc.target/powerpc/float128-minmax-2.c: New test.
Diff:
---
gcc/config/rs6000/rs6000.c | 11 +-
gcc/config/rs6000/rs6000.h | 5 -
gcc/config/rs6000/rs6000.md | 197 +++++++--------------
gcc/testsuite/gcc.target/powerpc/float128-cmove.c | 93 ----------
.../gcc.target/powerpc/float128-minmax-2.c | 15 --
.../gcc.target/powerpc/float128-minmax-3.c | 15 --
6 files changed, 67 insertions(+), 269 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index ca3c7cb6020..03379260472 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -15922,8 +15922,8 @@ rs6000_emit_vector_cond_expr (rtx dest, rtx op_true, rtx op_false,
return 1;
}
-/* Possibly emit the xsmaxc{dp,qp} and xsminc{dp,qp} instructions to emit a
- maximum or minimum with "C" semantics.
+/* Possibly emit the xsmaxcdp and xsmincdp instructions to emit a maximum or
+ minimum with "C" semantics.
Unless you use -ffast-math, you can't use these instructions to replace
conditions that implicitly reverse the condition because the comparison
@@ -16059,10 +16059,6 @@ have_compare_and_set_mask (machine_mode mode)
case E_DFmode:
return TARGET_P9_MINMAX;
- case E_KFmode:
- case E_TFmode:
- return FLOAT128_MIN_MAX_FPMASK_P (mode);
-
default:
break;
}
@@ -16331,8 +16327,7 @@ rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
/* VSX/altivec have direct min/max insns. */
if ((code == SMAX || code == SMIN)
&& (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
- || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))
- || FLOAT128_MIN_MAX_FPMASK_P (mode)))
+ || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
{
emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1)));
return;
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 520e277f7f3..f5f7ac3f209 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -345,11 +345,6 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
|| ((MODE) == TDmode) \
|| (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE)))
-/* Macro whether the float128 minimum, maximum, and set compare mask
- instructions are enabled. */
-#define FLOAT128_MIN_MAX_FPMASK_P(MODE) \
- (TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (MODE))
-
/* Return true for floating point that does not use a vector register. */
#define SCALAR_FLOAT_MODE_NOT_VECTOR_P(MODE) \
(SCALAR_FLOAT_MODE_P (MODE) && !FLOAT128_VECTOR_P (MODE))
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index cd292a798cb..a5ab96f00bc 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -575,19 +575,6 @@
; And again, for when we need two FP modes in a pattern.
(define_mode_iterator SFDF2 [SF DF])
-; Floating scalars that supports the set compare mask instruction.
-(define_mode_iterator FPMASK [SF
- DF
- (KF "FLOAT128_MIN_MAX_FPMASK_P (KFmode)")
- (TF "FLOAT128_MIN_MAX_FPMASK_P (TFmode)")])
-
-; And again, for patterns that need two (potentially) different floating point
-; scalars that support the set compare mask instruction.
-(define_mode_iterator FPMASK2 [SF
- DF
- (KF "FLOAT128_MIN_MAX_FPMASK_P (KFmode)")
- (TF "FLOAT128_MIN_MAX_FPMASK_P (TFmode)")])
-
; A generic s/d attribute, for sp/dp for example.
(define_mode_attr sd [(SF "s") (DF "d")
(V4SF "s") (V2DF "d")])
@@ -621,13 +608,8 @@
; SF/DF constraint for arithmetic on VSX registers using instructions added in
; ISA 2.06 (power7). This includes instructions that normally target DF mode,
; but are used on SFmode, since internally SFmode values are kept in the DFmode
-; format. Also include IEEE 128-bit instructions which are restricted to the
-; Altivec registers.
-(define_mode_attr Fv [(SF "wa")
- (DF "wa")
- (DI "wa")
- (KF "v")
- (TF "v")])
+; format.
+(define_mode_attr Fv [(SF "wa") (DF "wa") (DI "wa")])
; Which isa is needed for those float instructions?
(define_mode_attr Fisa [(SF "p8v") (DF "*") (DI "*")])
@@ -5212,17 +5194,6 @@
}
[(set_attr "type" "fp")])
-;; Min/max for ISA 3.1 IEEE 128-bit floating point
-(define_insn "s<minmax><mode>3"
- [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
- (fp_minmax:IEEE128
- (match_operand:IEEE128 1 "altivec_register_operand" "v")
- (match_operand:IEEE128 2 "altivec_register_operand" "v")))]
- "TARGET_POWER10"
- "xs<minmax>cqp %0,%1,%2"
- [(set_attr "type" "vecfloat")
- (set_attr "size" "128")])
-
;; The conditional move instructions allow us to perform max and min operations
;; even when we don't have the appropriate max/min instruction using the FSEL
;; instruction.
@@ -5334,10 +5305,10 @@
;; Floating point conditional move
(define_expand "mov<mode>cc"
- [(set (match_operand:FPMASK 0 "gpc_reg_operand")
- (if_then_else:FPMASK (match_operand 1 "comparison_operator")
- (match_operand:FPMASK 2 "gpc_reg_operand")
- (match_operand:FPMASK 3 "gpc_reg_operand")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand")
+ (if_then_else:SFDF (match_operand 1 "comparison_operator")
+ (match_operand:SFDF 2 "gpc_reg_operand")
+ (match_operand:SFDF 3 "gpc_reg_operand")))]
"TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT"
{
if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
@@ -5357,132 +5328,92 @@
"fsel %0,%1,%2,%3"
[(set_attr "type" "fp")])
-(define_insn_and_split "*mov<FPMASK:mode><FPMASK2:mode>cc_fpmask"
- [(set (match_operand:FPMASK 0 "vsx_register_operand" "=<FPMASK:Fv>")
- (if_then_else:FPMASK
+(define_insn_and_split "*mov<SFDF:mode><SFDF2:mode>cc_p9"
+ [(set (match_operand:SFDF 0 "vsx_register_operand" "=&<SFDF:Fv>,<SFDF:Fv>")
+ (if_then_else:SFDF
(match_operator:CCFP 1 "fpmask_comparison_operator"
- [(match_operand:FPMASK2 2 "vsx_register_operand" "<FPMASK2:Fv>")
- (match_operand:FPMASK2 3 "vsx_register_operand" "<FPMASK2:Fv>")])
- (match_operand:FPMASK 4 "vsx_register_operand" "<FPMASK:Fv>")
- (match_operand:FPMASK 5 "vsx_register_operand" "<FPMASK:Fv>")))
- (clobber (match_scratch:V2DI 6 "=&<FPMASK2:Fv>"))]
+ [(match_operand:SFDF2 2 "vsx_register_operand" "<SFDF2:Fv>,<SFDF2:Fv>")
+ (match_operand:SFDF2 3 "vsx_register_operand" "<SFDF2:Fv>,<SFDF2:Fv>")])
+ (match_operand:SFDF 4 "vsx_register_operand" "<SFDF:Fv>,<SFDF:Fv>")
+ (match_operand:SFDF 5 "vsx_register_operand" "<SFDF:Fv>,<SFDF:Fv>")))
+ (clobber (match_scratch:V2DI 6 "=0,&wa"))]
"TARGET_P9_MINMAX"
"#"
"&& 1"
- [(pc)]
+ [(set (match_dup 6)
+ (if_then_else:V2DI (match_dup 1)
+ (match_dup 7)
+ (match_dup 8)))
+ (set (match_dup 0)
+ (if_then_else:SFDF (ne (match_dup 6)
+ (match_dup 8))
+ (match_dup 4)
+ (match_dup 5)))]
{
- rtx dest = operands[0];
- rtx cmp = operands[1];
- rtx cmp_op1 = operands[2];
- rtx cmp_op2 = operands[3];
- rtx move_t = operands[4];
- rtx move_f = operands[5];
- rtx mask_reg = operands[6];
- rtx mask_m1 = CONSTM1_RTX (V2DImode);
- rtx mask_0 = CONST0_RTX (V2DImode);
- machine_mode move_mode = <FPMASK:MODE>mode;
- machine_mode compare_mode = <FPMASK2:MODE>mode;
-
- if (GET_CODE (mask_reg) == SCRATCH)
- mask_reg = gen_reg_rtx (V2DImode);
-
- /* Emit the compare and set mask instruction. */
- emit_insn (gen_fpmask<FPMASK2:mode> (mask_reg, cmp, cmp_op1, cmp_op2,
- mask_m1, mask_0));
-
- /* If we have a 64-bit comparison, but an 128-bit move, we need to extend the
- mask. Because we are using the splat builtin to extend the V2DImode, we
- need to use element 1 on little endian systems. */
- if (!FLOAT128_IEEE_P (compare_mode) && FLOAT128_IEEE_P (move_mode))
- {
- rtx element = WORDS_BIG_ENDIAN ? const0_rtx : const1_rtx;
- emit_insn (gen_vsx_xxspltd_v2di (mask_reg, mask_reg, element));
- }
+ if (GET_CODE (operands[6]) == SCRATCH)
+ operands[6] = gen_reg_rtx (V2DImode);
- /* Now emit the XXSEL insn. */
- emit_insn (gen_xxsel<FPMASK:mode> (dest, mask_reg, mask_0, move_t, move_f));
- DONE;
+ operands[7] = CONSTM1_RTX (V2DImode);
+ operands[8] = CONST0_RTX (V2DImode);
}
- ;; length is 12 in case we need to add XXPERMDI
- [(set_attr "length" "12")
+ [(set_attr "length" "8")
(set_attr "type" "vecperm")])
;; Handle inverting the fpmask comparisons.
-(define_insn_and_split "*mov<FPMASK:mode><FPMASK2:mode>cc_invert_fpmask"
- [(set (match_operand:FPMASK 0 "vsx_register_operand" "=<FPMASK:Fv>")
- (if_then_else:FPMASK
+(define_insn_and_split "*mov<SFDF:mode><SFDF2:mode>cc_invert_p9"
+ [(set (match_operand:SFDF 0 "vsx_register_operand" "=&<SFDF:Fv>,<SFDF:Fv>")
+ (if_then_else:SFDF
(match_operator:CCFP 1 "invert_fpmask_comparison_operator"
- [(match_operand:FPMASK2 2 "vsx_register_operand" "<FPMASK2:Fv>")
- (match_operand:FPMASK2 3 "vsx_register_operand" "<FPMASK2:Fv>")])
- (match_operand:FPMASK 4 "vsx_register_operand" "<FPMASK:Fv>")
- (match_operand:FPMASK 5 "vsx_register_operand" "<FPMASK:Fv>")))
- (clobber (match_scratch:V2DI 6 "=&<FPMASK2:Fv>"))]
+ [(match_operand:SFDF2 2 "vsx_register_operand" "<SFDF2:Fv>,<SFDF2:Fv>")
+ (match_operand:SFDF2 3 "vsx_register_operand" "<SFDF2:Fv>,<SFDF2:Fv>")])
+ (match_operand:SFDF 4 "vsx_register_operand" "<SFDF:Fv>,<SFDF:Fv>")
+ (match_operand:SFDF 5 "vsx_register_operand" "<SFDF:Fv>,<SFDF:Fv>")))
+ (clobber (match_scratch:V2DI 6 "=0,&wa"))]
"TARGET_P9_MINMAX"
"#"
"&& 1"
- [(pc)]
+ [(set (match_dup 6)
+ (if_then_else:V2DI (match_dup 9)
+ (match_dup 7)
+ (match_dup 8)))
+ (set (match_dup 0)
+ (if_then_else:SFDF (ne (match_dup 6)
+ (match_dup 8))
+ (match_dup 5)
+ (match_dup 4)))]
{
- rtx dest = operands[0];
- rtx old_cmp = operands[1];
- rtx cmp_op1 = operands[2];
- rtx cmp_op2 = operands[3];
- enum rtx_code cond = reverse_condition_maybe_unordered (GET_CODE (old_cmp));
- rtx cmp_rev = gen_rtx_fmt_ee (cond, CCFPmode, cmp_op1, cmp_op2);
- rtx move_f = operands[4];
- rtx move_t = operands[5];
- rtx mask_reg = operands[6];
- rtx mask_m1 = CONSTM1_RTX (V2DImode);
- rtx mask_0 = CONST0_RTX (V2DImode);
- machine_mode move_mode = <FPMASK:MODE>mode;
- machine_mode compare_mode = <FPMASK2:MODE>mode;
-
- if (GET_CODE (mask_reg) == SCRATCH)
- mask_reg = gen_reg_rtx (V2DImode);
+ rtx op1 = operands[1];
+ enum rtx_code cond = reverse_condition_maybe_unordered (GET_CODE (op1));
- /* Emit the compare and set mask instruction. */
- emit_insn (gen_fpmask<FPMASK2:mode> (mask_reg, cmp_rev, cmp_op1, cmp_op2,
- mask_m1, mask_0));
+ if (GET_CODE (operands[6]) == SCRATCH)
+ operands[6] = gen_reg_rtx (V2DImode);
- /* If we have a 64-bit comparison, but an 128-bit move, we need to extend the
- mask. Because we are using the splat builtin to extend the V2DImode, we
- need to use element 1 on little endian systems. */
- if (!FLOAT128_IEEE_P (compare_mode) && FLOAT128_IEEE_P (move_mode))
- {
- rtx element = WORDS_BIG_ENDIAN ? const0_rtx : const1_rtx;
- emit_insn (gen_vsx_xxspltd_v2di (mask_reg, mask_reg, element));
- }
+ operands[7] = CONSTM1_RTX (V2DImode);
+ operands[8] = CONST0_RTX (V2DImode);
- /* Now emit the XXSEL insn. */
- emit_insn (gen_xxsel<FPMASK:mode> (dest, mask_reg, mask_0, move_t, move_f));
- DONE;
+ operands[9] = gen_rtx_fmt_ee (cond, CCFPmode, operands[2], operands[3]);
}
- ;; length is 12 in case we need to add XXPERMDI
- [(set_attr "length" "12")
+ [(set_attr "length" "8")
(set_attr "type" "vecperm")])
-(define_insn "fpmask<mode>"
- [(set (match_operand:V2DI 0 "vsx_register_operand" "=<Fv>")
+(define_insn "*fpmask<mode>"
+ [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa")
(if_then_else:V2DI
(match_operator:CCFP 1 "fpmask_comparison_operator"
- [(match_operand:FPMASK 2 "vsx_register_operand" "<Fv>")
- (match_operand:FPMASK 3 "vsx_register_operand" "<Fv>")])
+ [(match_operand:SFDF 2 "vsx_register_operand" "<Fv>")
+ (match_operand:SFDF 3 "vsx_register_operand" "<Fv>")])
(match_operand:V2DI 4 "all_ones_constant" "")
(match_operand:V2DI 5 "zero_constant" "")))]
"TARGET_P9_MINMAX"
-{
- return (FLOAT128_IEEE_P (<MODE>mode)
- ? "xscmp%V1qp %0,%2,%3"
- : "xscmp%V1dp %x0,%x2,%x3");
-}
+ "xscmp%V1dp %x0,%x2,%x3"
[(set_attr "type" "fpcompare")])
-(define_insn "xxsel<mode>"
- [(set (match_operand:FPMASK 0 "vsx_register_operand" "=wa")
- (if_then_else:FPMASK
- (ne (match_operand:V2DI 1 "vsx_register_operand" "wa")
- (match_operand:V2DI 2 "zero_constant" ""))
- (match_operand:FPMASK 3 "vsx_register_operand" "wa")
- (match_operand:FPMASK 4 "vsx_register_operand" "wa")))]
+(define_insn "*xxsel<mode>"
+ [(set (match_operand:SFDF 0 "vsx_register_operand" "=<Fv>")
+ (if_then_else:SFDF (ne (match_operand:V2DI 1 "vsx_register_operand" "wa")
+ (match_operand:V2DI 2 "zero_constant" ""))
+ (match_operand:SFDF 3 "vsx_register_operand" "<Fv>")
+ (match_operand:SFDF 4 "vsx_register_operand" "<Fv>")))]
"TARGET_P9_MINMAX"
"xxsel %x0,%x4,%x3,%x1"
[(set_attr "type" "vecmove")])
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-cmove.c b/gcc/testsuite/gcc.target/powerpc/float128-cmove.c
deleted file mode 100644
index 639d5a77087..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/float128-cmove.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target ppc_float128_hw } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-/* { dg-final { scan-assembler {\mxscmpeq[dq]p\M} } } */
-/* { dg-final { scan-assembler {\mxxpermdi\M} } } */
-/* { dg-final { scan-assembler {\mxxsel\M} } } */
-/* { dg-final { scan-assembler-not {\mxscmpu[dq]p\M} } } */
-/* { dg-final { scan-assembler-not {\mfcmp[uo]\M} } } */
-/* { dg-final { scan-assembler-not {\mfsel\M} } } */
-
-/* This series of tests tests whether you can do a conditional move where the
- test is one floating point type, and the result is another floating point
- type.
-
- If the comparison type is SF/DFmode, and the move type is IEEE 128-bit
- floating point, we have to duplicate the mask in the lower 64-bits with
- XXPERMDI because XSCMPEQDP clears the bottom 64-bits of the mask register.
-
- Going the other way (IEEE 128-bit comparsion, 64-bit move) is fine as the
- mask word will be 128-bits. */
-
-float
-eq_f_d (float a, float b, double x, double y)
-{
- return (x == y) ? a : b;
-}
-
-double
-eq_d_f (double a, double b, float x, float y)
-{
- return (x == y) ? a : b;
-}
-
-float
-eq_f_f128 (float a, float b, __float128 x, __float128 y)
-{
- return (x == y) ? a : b;
-}
-
-double
-eq_d_f128 (double a, double b, __float128 x, __float128 y)
-{
- return (x == y) ? a : b;
-}
-
-__float128
-eq_f128_f (__float128 a, __float128 b, float x, float y)
-{
- return (x == y) ? a : b;
-}
-
-__float128
-eq_f128_d (__float128 a, __float128 b, double x, double y)
-{
- return (x != y) ? a : b;
-}
-
-float
-ne_f_d (float a, float b, double x, double y)
-{
- return (x != y) ? a : b;
-}
-
-double
-ne_d_f (double a, double b, float x, float y)
-{
- return (x != y) ? a : b;
-}
-
-float
-ne_f_f128 (float a, float b, __float128 x, __float128 y)
-{
- return (x != y) ? a : b;
-}
-
-double
-ne_d_f128 (double a, double b, __float128 x, __float128 y)
-{
- return (x != y) ? a : b;
-}
-
-__float128
-ne_f128_f (__float128 a, __float128 b, float x, float y)
-{
- return (x != y) ? a : b;
-}
-
-__float128
-ne_f128_d (__float128 a, __float128 b, double x, double y)
-{
- return (x != y) ? a : b;
-}
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c b/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c
deleted file mode 100644
index c71ba08c9f8..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/* { dg-require-effective-target ppc_float128_hw } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -ffast-math" } */
-
-#ifndef TYPE
-#define TYPE _Float128
-#endif
-
-/* Test that the fminf128/fmaxf128 functions generate if/then/else and not a
- call. */
-TYPE f128_min (TYPE a, TYPE b) { return __builtin_fminf128 (a, b); }
-TYPE f128_max (TYPE a, TYPE b) { return __builtin_fmaxf128 (a, b); }
-
-/* { dg-final { scan-assembler {\mxsmaxcqp\M} } } */
-/* { dg-final { scan-assembler {\mxsmincqp\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-minmax-3.c b/gcc/testsuite/gcc.target/powerpc/float128-minmax-3.c
deleted file mode 100644
index 6f7627c0f2a..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/float128-minmax-3.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/* { dg-require-effective-target ppc_float128_hw } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#ifndef TYPE
-#define TYPE _Float128
-#endif
-
-/* Test that the fminf128/fmaxf128 functions generate if/then/else and not a
- call. */
-TYPE f128_min (TYPE a, TYPE b) { return (a < b) ? a : b; }
-TYPE f128_max (TYPE a, TYPE b) { return (b > a) ? b : a; }
-
-/* { dg-final { scan-assembler {\mxsmaxcqp\M} } } */
-/* { dg-final { scan-assembler {\mxsmincqp\M} } } */
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