[gcc(refs/users/meissner/heads/work048)] Add IEEE 128-bit min/max support on PowerPC.

[gcc(refs/users/meissner/heads/work048)] Add IEEE 128-bit min/max support on PowerPC.

[Michael Meissner]

https://gcc.gnu.org/g:035087231f53f564a3583091e261033e49ad39f8

commit 035087231f53f564a3583091e261033e49ad39f8
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Apr 14 15:53:29 2021 -0400

    Add IEEE 128-bit min/max support on PowerPC.
    
    This patch adds the support for the IEEE 128-bit floating point C minimum and
    maximum instructions.  The next patch will add the support for using the
    compare and set mask instruction to implement conditional moves.
    
    Rather than trying to overload the current SF/DF min/max support, it was
    simpler to just provide the new instructions as a separate insn.
    
    gcc/
    2021-04-14  Michael Meissner  <meissner@linux.ibm.com>
    
            * config/rs6000/rs6000.c (rs6000_emit_minmax): Add support for ISA
            3.1 IEEE 128-bit floating point xsmaxcqp and xsmincqp instructions.
            * config/rs6000/rs6000.md (s<minmax><mode>3, IEEE128 iterator):
            New insns.
    
    gcc/testsuite/
    2021-04-14  Michael Meissner  <meissner@linux.ibm.com>
    
            * gcc.target/powerpc/float128-minmax-2.c: New test.

Diff:
---
 gcc/config/rs6000/rs6000.c                           |  3 ++-
 gcc/config/rs6000/rs6000.md                          | 11 +++++++++++
 gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c | 15 +++++++++++++++
 3 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 48b8efd732b..8d00f99e9fd 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -16111,7 +16111,8 @@ rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
   /* VSX/altivec have direct min/max insns.  */
   if ((code == SMAX || code == SMIN)
       && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
-	  || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
+	  || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))
+	  || (TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode))))
     {
       emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1)));
       return;
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index c8cdc42533c..17b2fdc1cdd 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5194,6 +5194,17 @@
 }
   [(set_attr "type" "fp")])
 
+;; Min/max for ISA 3.1 IEEE 128-bit floating point
+(define_insn "s<minmax><mode>3"
+  [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
+	(fp_minmax:IEEE128
+	 (match_operand:IEEE128 1 "altivec_register_operand" "v")
+	 (match_operand:IEEE128 2 "altivec_register_operand" "v")))]
+  "TARGET_POWER10"
+  "xs<minmax>cqp %0,%1,%2"
+  [(set_attr "type" "vecfloat")
+   (set_attr "size" "128")])
+
 ;; The conditional move instructions allow us to perform max and min operations
 ;; even when we don't have the appropriate max/min instruction using the FSEL
 ;; instruction.
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c b/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c
new file mode 100644
index 00000000000..c71ba08c9f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c
@@ -0,0 +1,15 @@
+/* { dg-require-effective-target ppc_float128_hw } */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2 -ffast-math" } */
+
+#ifndef TYPE
+#define TYPE _Float128
+#endif
+
+/* Test that the fminf128/fmaxf128 functions generate if/then/else and not a
+   call.  */
+TYPE f128_min (TYPE a, TYPE b) { return __builtin_fminf128 (a, b); }
+TYPE f128_max (TYPE a, TYPE b) { return __builtin_fmaxf128 (a, b); }
+
+/* { dg-final { scan-assembler {\mxsmaxcqp\M} } } */
+/* { dg-final { scan-assembler {\mxsmincqp\M} } } */