public inbox for gcc-cvs@sourceware.org
help / color / mirror / Atom feed
* [gcc(refs/users/clyon/heads/mve-autovec)] arm: MVE: Factorize all vcmp* integer patterns
@ 2021-04-21 13:47 Christophe Lyon
0 siblings, 0 replies; 2+ messages in thread
From: Christophe Lyon @ 2021-04-21 13:47 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:1dac72378bb8cbc02352df75734d068e7dba67ae
commit 1dac72378bb8cbc02352df75734d068e7dba67ae
Author: Christophe Lyon <christophe.lyon@linaro.org>
Date: Wed Feb 24 19:58:58 2021 +0000
arm: MVE: Factorize all vcmp* integer patterns
After removing the signed and unsigned suffixes in the previous
patches, we can now factorize the vcmp* patterns: there is no longer
an asymmetry where operators do not have the same set of signed and
unsigned variants.
The will make maintenance easier.
MVE has a different set of vector comparison operators than Neon,
so we have to introduce dedicated iterators.
2021-03-01 Christophe Lyon <christophe.lyon@linaro.org>
gcc/
* config/arm/iterators.md (MVE_COMPARISONS): New.
(mve_cmp_op): New.
(mve_cmp_type): New.
* config/arm/mve.md (mve_vcmp<mve_cmp_op>q_<mode>): New, merge all
mve_vcmp patterns.
(mve_vcmpneq_<mode>, mve_vcmpcsq_n_<mode>, mve_vcmpcsq_<mode>)
(mve_vcmpeqq_n_<mode>, mve_vcmpeqq_<mode>, mve_vcmpgeq_n_<mode>)
(mve_vcmpgeq_<mode>, mve_vcmpgtq_n_<mode>, mve_vcmpgtq_<mode>)
(mve_vcmphiq_n_<mode>, mve_vcmphiq_<mode>, mve_vcmpleq_n_<mode>)
(mve_vcmpleq_<mode>, mve_vcmpltq_n_<mode>, mve_vcmpltq_<mode>)
(mve_vcmpneq_n_<mode>, mve_vcmpltq_n_<mode>, mve_vcmpltq_<mode>)
(mve_vcmpneq_n_<mode>): Remove.
Diff:
---
gcc/config/arm/iterators.md | 8 ++
gcc/config/arm/mve.md | 250 ++++----------------------------------------
2 files changed, 27 insertions(+), 231 deletions(-)
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 0aba93f5522..29347f70bcd 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -285,6 +285,8 @@
;; Comparisons for vc<cmp>
(define_code_iterator COMPARISONS [eq gt ge le lt])
+;; Comparisons for MVE
+(define_code_iterator MVE_COMPARISONS [eq ge geu gt gtu le lt ne])
;; A list of ...
(define_code_iterator IOR_XOR [ior xor])
@@ -336,8 +338,14 @@
(define_code_attr cmp_op [(eq "eq") (gt "gt") (ge "ge") (lt "lt") (le "le")
(gtu "gt") (geu "ge")])
+(define_code_attr mve_cmp_op [(eq "eq") (gt "gt") (ge "ge") (lt "lt") (le "le")
+ (gtu "hi") (geu "cs") (ne "ne")])
+
(define_code_attr cmp_type [(eq "i") (gt "s") (ge "s") (lt "s") (le "s")])
+(define_code_attr mve_cmp_type [(eq "i") (gt "s") (ge "s") (lt "s") (le "s")
+ (gtu "u") (geu "u") (ne "i")])
+
(define_code_attr vfml_op [(plus "a") (minus "s")])
(define_code_attr ss_op [(ss_plus "qadd") (ss_minus "qsub")])
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index e9f095d2d10..40baff7149f 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -836,17 +836,30 @@
(set_attr "length""8")])
;;
-;; [vcmpneq_])
+;; [vcmpneq_, vcmpcsq_, vcmpeqq_, vcmpgeq_, vcmpgtq_, vcmphiq_, vcmpleq_, vcmpltq_])
;;
-(define_insn "mve_vcmpneq_<mode>"
+(define_insn "mve_vcmp<mve_cmp_op>q_<mode>"
[
(set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VCMPNEQ))
+ (MVE_COMPARISONS:HI (match_operand:MVE_2 1 "s_register_operand" "w")
+ (match_operand:MVE_2 2 "s_register_operand" "w")))
+ ]
+ "TARGET_HAVE_MVE"
+ "vcmp.<mve_cmp_type>%#<V_sz_elem> <mve_cmp_op>, %q1, %q2"
+ [(set_attr "type" "mve_move")
+])
+
+;;
+;; [vcmpcsq_n_, vcmpeqq_n_, vcmpgeq_n_, vcmpgtq_n_, vcmphiq_n_, vcmpleq_n_, vcmpltq_n_, vcmpneq_n_])
+;;
+(define_insn "mve_vcmp<mve_cmp_op>q_n_<mode>"
+ [
+ (set (match_operand:HI 0 "vpr_register_operand" "=Up")
+ (MVE_COMPARISONS:HI (match_operand:MVE_2 1 "s_register_operand" "w")
+ (match_operand:<V_elem> 2 "s_register_operand" "r")))
]
"TARGET_HAVE_MVE"
- "vcmp.i%#<V_sz_elem> ne, %q1, %q2"
+ "vcmp.<mve_cmp_type>%#<V_sz_elem> <mve_cmp_op>, %q1, %2"
[(set_attr "type" "mve_move")
])
@@ -1004,231 +1017,6 @@
"TARGET_HAVE_MVE && !BYTES_BIG_ENDIAN"
)
-;;
-;; [vcmpcsq_n_])
-;;
-(define_insn "mve_vcmpcsq_n_<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VCMPCSQ_N_U))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.u%#<V_sz_elem> cs, %q1, %2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpcsq_])
-;;
-(define_insn "mve_vcmpcsq_<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VCMPCSQ_U))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.u%#<V_sz_elem> cs, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpeqq_n_])
-;;
-(define_insn "mve_vcmpeqq_n_<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VCMPEQQ_N))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.i%#<V_sz_elem> eq, %q1, %2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpeqq_])
-;;
-(define_insn "mve_vcmpeqq_<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VCMPEQQ))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.i%#<V_sz_elem> eq, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpgeq_n_])
-;;
-(define_insn "mve_vcmpgeq_n_<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VCMPGEQ_N_S))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.s%#<V_sz_elem> ge, %q1, %2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpgeq_])
-;;
-(define_insn "mve_vcmpgeq_<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VCMPGEQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.s%#<V_sz_elem> ge, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpgtq_n_])
-;;
-(define_insn "mve_vcmpgtq_n_<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VCMPGTQ_N_S))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.s%#<V_sz_elem> gt, %q1, %2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpgtq_])
-;;
-(define_insn "mve_vcmpgtq_<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VCMPGTQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.s%#<V_sz_elem> gt, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmphiq_n_])
-;;
-(define_insn "mve_vcmphiq_n_<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VCMPHIQ_N_U))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.u%#<V_sz_elem> hi, %q1, %2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmphiq_])
-;;
-(define_insn "mve_vcmphiq_<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VCMPHIQ_U))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.u%#<V_sz_elem> hi, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpleq_n_])
-;;
-(define_insn "mve_vcmpleq_n_<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VCMPLEQ_N_S))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.s%#<V_sz_elem> le, %q1, %2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpleq_])
-;;
-(define_insn "mve_vcmpleq_<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VCMPLEQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.s%#<V_sz_elem> le, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpltq_n_])
-;;
-(define_insn "mve_vcmpltq_n_<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VCMPLTQ_N_S))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.s%#<V_sz_elem> lt, %q1, %2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpltq_])
-;;
-(define_insn "mve_vcmpltq_<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VCMPLTQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.s%#<V_sz_elem> lt, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpneq_n_])
-;;
-(define_insn "mve_vcmpneq_n_<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VCMPNEQ_N))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.i%#<V_sz_elem> ne, %q1, %2"
- [(set_attr "type" "mve_move")
-])
-
;;
;; [veorq_u, veorq_s])
;;
^ permalink raw reply [flat|nested] 2+ messages in thread
* [gcc(refs/users/clyon/heads/mve-autovec)] arm: MVE: Factorize all vcmp* integer patterns
@ 2021-03-15 16:25 Christophe Lyon
0 siblings, 0 replies; 2+ messages in thread
From: Christophe Lyon @ 2021-03-15 16:25 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:6b2b5264f1b790f8c4ecb940afe7311a211084c7
commit 6b2b5264f1b790f8c4ecb940afe7311a211084c7
Author: Christophe Lyon <christophe.lyon@linaro.org>
Date: Wed Feb 24 19:58:58 2021 +0000
arm: MVE: Factorize all vcmp* integer patterns
After removing the signed and unsigned suffixes in the previous
patches, we can now factorize the vcmp* patterns: there is no longer
an asymmetry where operators do not have the same set of signed and
unsigned variants.
The will make maintenance easier.
MVE has a different set of vector comparison operators than Neon,
so we have to introduce dedicated iterators.
2021-03-01 Christophe Lyon <christophe.lyon@linaro.org>
gcc/
* config/arm/iterators.md (MVE_COMPARISONS): New.
(mve_cmp_op): New.
(mve_cmp_type): New.
* config/arm/mve.md (mve_vcmp<mve_cmp_op>q_<mode>): New, merge all
mve_vcmp patterns.
(mve_vcmpneq_<mode>, mve_vcmpcsq_n_<mode>, mve_vcmpcsq_<mode>)
(mve_vcmpeqq_n_<mode>, mve_vcmpeqq_<mode>, mve_vcmpgeq_n_<mode>)
(mve_vcmpgeq_<mode>, mve_vcmpgtq_n_<mode>, mve_vcmpgtq_<mode>)
(mve_vcmphiq_n_<mode>, mve_vcmphiq_<mode>, mve_vcmpleq_n_<mode>)
(mve_vcmpleq_<mode>, mve_vcmpltq_n_<mode>, mve_vcmpltq_<mode>)
(mve_vcmpneq_n_<mode>, mve_vcmpltq_n_<mode>, mve_vcmpltq_<mode>)
(mve_vcmpneq_n_<mode>): Remove.
Diff:
---
gcc/config/arm/iterators.md | 8 ++
gcc/config/arm/mve.md | 250 ++++----------------------------------------
2 files changed, 27 insertions(+), 231 deletions(-)
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 52219228305..5bfae065e49 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -284,6 +284,8 @@
;; Comparisons for vc<cmp>
(define_code_iterator COMPARISONS [eq gt ge le lt])
+;; Comparisons for MVE
+(define_code_iterator MVE_COMPARISONS [eq ge geu gt gtu le lt ne])
;; A list of ...
(define_code_iterator IOR_XOR [ior xor])
@@ -335,8 +337,14 @@
(define_code_attr cmp_op [(eq "eq") (gt "gt") (ge "ge") (lt "lt") (le "le")
(gtu "gt") (geu "ge")])
+(define_code_attr mve_cmp_op [(eq "eq") (gt "gt") (ge "ge") (lt "lt") (le "le")
+ (gtu "hi") (geu "cs") (ne "ne")])
+
(define_code_attr cmp_type [(eq "i") (gt "s") (ge "s") (lt "s") (le "s")])
+(define_code_attr mve_cmp_type [(eq "i") (gt "s") (ge "s") (lt "s") (le "s")
+ (gtu "u") (geu "u") (ne "i")])
+
(define_code_attr vfml_op [(plus "a") (minus "s")])
(define_code_attr ss_op [(ss_plus "qadd") (ss_minus "qsub")])
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 45dc8dd189f..c3f9d81283f 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -840,17 +840,30 @@
(set_attr "length""8")])
;;
-;; [vcmpneq_])
+;; [vcmpneq_, vcmpcsq_, vcmpeqq_, vcmpgeq_, vcmpgtq_, vcmphiq_, vcmpleq_, vcmpltq_])
;;
-(define_insn "mve_vcmpneq_<mode>"
+(define_insn "mve_vcmp<mve_cmp_op>q_<mode>"
[
(set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VCMPNEQ))
+ (MVE_COMPARISONS:HI (match_operand:MVE_2 1 "s_register_operand" "w")
+ (match_operand:MVE_2 2 "s_register_operand" "w")))
+ ]
+ "TARGET_HAVE_MVE"
+ "vcmp.<mve_cmp_type>%#<V_sz_elem> <mve_cmp_op>, %q1, %q2"
+ [(set_attr "type" "mve_move")
+])
+
+;;
+;; [vcmpcsq_n_, vcmpeqq_n_, vcmpgeq_n_, vcmpgtq_n_, vcmphiq_n_, vcmpleq_n_, vcmpltq_n_, vcmpneq_n_])
+;;
+(define_insn "mve_vcmp<mve_cmp_op>q_n_<mode>"
+ [
+ (set (match_operand:HI 0 "vpr_register_operand" "=Up")
+ (MVE_COMPARISONS:HI (match_operand:MVE_2 1 "s_register_operand" "w")
+ (match_operand:<V_elem> 2 "s_register_operand" "r")))
]
"TARGET_HAVE_MVE"
- "vcmp.i%#<V_sz_elem> ne, %q1, %q2"
+ "vcmp.<mve_cmp_type>%#<V_sz_elem> <mve_cmp_op>, %q1, %2"
[(set_attr "type" "mve_move")
])
@@ -1008,231 +1021,6 @@
"TARGET_HAVE_MVE && !BYTES_BIG_ENDIAN"
)
-;;
-;; [vcmpcsq_n_])
-;;
-(define_insn "mve_vcmpcsq_n_<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VCMPCSQ_N_U))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.u%#<V_sz_elem> cs, %q1, %2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpcsq_])
-;;
-(define_insn "mve_vcmpcsq_<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VCMPCSQ_U))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.u%#<V_sz_elem> cs, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpeqq_n_])
-;;
-(define_insn "mve_vcmpeqq_n_<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VCMPEQQ_N))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.i%#<V_sz_elem> eq, %q1, %2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpeqq_])
-;;
-(define_insn "mve_vcmpeqq_<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VCMPEQQ))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.i%#<V_sz_elem> eq, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpgeq_n_])
-;;
-(define_insn "mve_vcmpgeq_n_<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VCMPGEQ_N_S))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.s%#<V_sz_elem> ge, %q1, %2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpgeq_])
-;;
-(define_insn "mve_vcmpgeq_<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VCMPGEQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.s%#<V_sz_elem> ge, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpgtq_n_])
-;;
-(define_insn "mve_vcmpgtq_n_<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VCMPGTQ_N_S))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.s%#<V_sz_elem> gt, %q1, %2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpgtq_])
-;;
-(define_insn "mve_vcmpgtq_<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VCMPGTQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.s%#<V_sz_elem> gt, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmphiq_n_])
-;;
-(define_insn "mve_vcmphiq_n_<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VCMPHIQ_N_U))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.u%#<V_sz_elem> hi, %q1, %2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmphiq_])
-;;
-(define_insn "mve_vcmphiq_<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VCMPHIQ_U))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.u%#<V_sz_elem> hi, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpleq_n_])
-;;
-(define_insn "mve_vcmpleq_n_<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VCMPLEQ_N_S))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.s%#<V_sz_elem> le, %q1, %2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpleq_])
-;;
-(define_insn "mve_vcmpleq_<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VCMPLEQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.s%#<V_sz_elem> le, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpltq_n_])
-;;
-(define_insn "mve_vcmpltq_n_<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VCMPLTQ_N_S))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.s%#<V_sz_elem> lt, %q1, %2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpltq_])
-;;
-(define_insn "mve_vcmpltq_<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VCMPLTQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.s%#<V_sz_elem> lt, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpneq_n_])
-;;
-(define_insn "mve_vcmpneq_n_<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VCMPNEQ_N))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.i%#<V_sz_elem> ne, %q1, %2"
- [(set_attr "type" "mve_move")
-])
-
;;
;; [veorq_u, veorq_s])
;;
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2021-04-21 13:47 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-04-21 13:47 [gcc(refs/users/clyon/heads/mve-autovec)] arm: MVE: Factorize all vcmp* integer patterns Christophe Lyon
-- strict thread matches above, loose matches on Subject: below --
2021-03-15 16:25 Christophe Lyon
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).