public inbox for gcc-cvs@sourceware.org
help / color / mirror / Atom feed
* [gcc(refs/users/meissner/heads/work049)] Move XXBLEND from altivec.md to vsx.md.
@ 2021-04-21 17:00 Michael Meissner
0 siblings, 0 replies; 3+ messages in thread
From: Michael Meissner @ 2021-04-21 17:00 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:2e2a3bd64e0a1f68d0534dfeffaa8ceac5405e76
commit 2e2a3bd64e0a1f68d0534dfeffaa8ceac5405e76
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 21 13:00:16 2021 -0400
Move XXBLEND from altivec.md to vsx.md.
This patch moves the XXBLEND support from altivec.md to vsx.md. Given
the instruction support all VSX registers, vsx.md is a more proper place
for this instruction.
In doing the move, I made changes to make it fit into the vsx.md
conventions. I changed the mode iterator from VM3 to VBLEND. I changed
the mode attribute from VM3_char to VBLEND_char.
I also changed the register_operand to the more specific
vsx_register_operand.
I was chatting with Pat Haugen, he said that the insn type should be
"vecperm" and not "vecsimple", so I changed this as well.
gcc/
2021-04-21 Michael Meissner <meissner@linux.ibm.com>
* config/rs6000/altivec.md (UNSPEC_XXBLEND): Move to vsx.md.
(VM3): Move to vsx.md.
(VM3_char): Move to vsx.md.
(xxblend_<mode>): Move to vsx.md.
* config/rs6000/vsx.md (UNSPEC_XXEVAL): Move from altivec.md.
(VM3): Move from altivec.md.
(VM3_char): Move from altivec.md.
(xxblend_<mode>): Move from altivec.md. Use vsx_register_operand
instead of register operand. Change the insn type from vecsimple
to vecperm.
Diff:
---
gcc/config/rs6000/altivec.md | 27 ---------------------------
gcc/config/rs6000/vsx.md | 28 ++++++++++++++++++++++++++++
2 files changed, 28 insertions(+), 27 deletions(-)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index a1ba10b0275..ed79a6b85cd 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -175,7 +175,6 @@
UNSPEC_VSTRIL
UNSPEC_SLDB
UNSPEC_SRDB
- UNSPEC_XXBLEND
])
(define_c_enum "unspecv"
@@ -216,21 +215,6 @@
(KF "FLOAT128_VECTOR_P (KFmode)")
(TF "FLOAT128_VECTOR_P (TFmode)")])
-;; Like VM2, just do char, short, int, long, float and double
-(define_mode_iterator VM3 [V4SI
- V8HI
- V16QI
- V4SF
- V2DF
- V2DI])
-
-(define_mode_attr VM3_char [(V2DI "d")
- (V4SI "w")
- (V8HI "h")
- (V16QI "b")
- (V2DF "d")
- (V4SF "w")])
-
;; Map the Vector convert single precision to double precision for integer
;; versus floating point
(define_mode_attr VS_sxwsp [(V4SI "sxw") (V4SF "sp")])
@@ -815,17 +799,6 @@
"vs<SLDB_lr>dbi %0,%1,%2,%3"
[(set_attr "type" "vecsimple")])
-(define_insn "xxblend_<mode>"
- [(set (match_operand:VM3 0 "register_operand" "=wa")
- (unspec:VM3 [(match_operand:VM3 1 "register_operand" "wa")
- (match_operand:VM3 2 "register_operand" "wa")
- (match_operand:VM3 3 "register_operand" "wa")]
- UNSPEC_XXBLEND))]
- "TARGET_POWER10"
- "xxblendv<VM3_char> %x0,%x1,%x2,%x3"
- [(set_attr "type" "vecsimple")
- (set_attr "prefixed" "yes")])
-
(define_expand "vstrir_<mode>"
[(set (match_operand:VIshort 0 "altivec_register_operand")
(unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand")]
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index d03ecd2946f..feab82b866a 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -271,6 +271,21 @@
;; and Vector Integer Multiply/Divide/Modulo Instructions
(define_mode_iterator VIlong [V2DI V4SI])
+;; Like VM2 in altivec.md, just do char, short, int, long, float and double
+(define_mode_iterator VM3 [V4SI
+ V8HI
+ V16QI
+ V4SF
+ V2DF
+ V2DI])
+
+(define_mode_attr VM3_char [(V2DI "d")
+ (V4SI "w")
+ (V8HI "h")
+ (V16QI "b")
+ (V2DF "d")
+ (V4SF "w")])
+
;; Constants for creating unspecs
(define_c_enum "unspec"
[UNSPEC_VSX_CONCAT
@@ -374,6 +389,7 @@
UNSPEC_XXSPLTI32DX_CONST
UNSPEC_XXPERMX
UNSPEC_XXEVAL
+ UNSPEC_XXBLEND
])
(define_int_iterator XVCVBF16 [UNSPEC_VSX_XVCVSPBF16
@@ -6525,3 +6541,15 @@
"xxeval %0,%1,%2,%3,%4"
[(set_attr "type" "vecperm")
(set_attr "prefixed" "yes")])
+
+;; XXBLEND support.
+(define_insn "xxblend_<mode>"
+ [(set (match_operand:VM3 0 "vsx_register_operand" "=wa")
+ (unspec:VM3 [(match_operand:VM3 1 "vsx_register_operand" "wa")
+ (match_operand:VM3 2 "vsx_register_operand" "wa")
+ (match_operand:VM3 3 "vsx_register_operand" "wa")]
+ UNSPEC_XXBLEND))]
+ "TARGET_POWER10"
+ "xxblendv<VM3_char> %x0,%x1,%x2,%x3"
+ [(set_attr "type" "vecperm")
+ (set_attr "prefixed" "yes")])
^ permalink raw reply [flat|nested] 3+ messages in thread
* [gcc(refs/users/meissner/heads/work049)] Move XXBLEND from altivec.md to vsx.md.
@ 2021-04-21 21:43 Michael Meissner
0 siblings, 0 replies; 3+ messages in thread
From: Michael Meissner @ 2021-04-21 21:43 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:3dd70a8f0dc5215cf8f26ffec65e76f5f27cf757
commit 3dd70a8f0dc5215cf8f26ffec65e76f5f27cf757
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 21 17:43:05 2021 -0400
Move XXBLEND from altivec.md to vsx.md.
This patch moves the XXBLEND support from altivec.md to vsx.md. Given
the instruction support all VSX registers, vsx.md is a more proper place
for this instruction.
In doing the move, I made changes to make it fit into the vsx.md
conventions. I changed the mode iterator from VM3 to VBLEND. I changed
the mode attribute from VM3_char to VBLEND_char.
I also changed the register_operand to the more specific
vsx_register_operand.
I was chatting with Pat Haugen, he said that the insn type should be
"vecperm" and not "vecsimple", so I changed this as well.
gcc/
2021-04-21 Michael Meissner <meissner@linux.ibm.com>
* config/rs6000/altivec.md (UNSPEC_XXBLEND): Move to vsx.md.
(VM3): Move to vsx.md.
(VM3_char): Move to vsx.md.
(xxblend_<mode>): Move to vsx.md.
* config/rs6000/vsx.md (UNSPEC_XXEVAL): Move from altivec.md.
(VM3): Move from altivec.md.
(VM3_char): Move from altivec.md.
(xxblend_<mode>): Move from altivec.md. Use vsx_register_operand
instead of register operand. Change the insn type from vecsimple
to vecperm.
Diff:
---
gcc/config/rs6000/altivec.md | 27 ---------------------------
gcc/config/rs6000/vsx.md | 28 ++++++++++++++++++++++++++++
2 files changed, 28 insertions(+), 27 deletions(-)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index a1ba10b0275..ed79a6b85cd 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -175,7 +175,6 @@
UNSPEC_VSTRIL
UNSPEC_SLDB
UNSPEC_SRDB
- UNSPEC_XXBLEND
])
(define_c_enum "unspecv"
@@ -216,21 +215,6 @@
(KF "FLOAT128_VECTOR_P (KFmode)")
(TF "FLOAT128_VECTOR_P (TFmode)")])
-;; Like VM2, just do char, short, int, long, float and double
-(define_mode_iterator VM3 [V4SI
- V8HI
- V16QI
- V4SF
- V2DF
- V2DI])
-
-(define_mode_attr VM3_char [(V2DI "d")
- (V4SI "w")
- (V8HI "h")
- (V16QI "b")
- (V2DF "d")
- (V4SF "w")])
-
;; Map the Vector convert single precision to double precision for integer
;; versus floating point
(define_mode_attr VS_sxwsp [(V4SI "sxw") (V4SF "sp")])
@@ -815,17 +799,6 @@
"vs<SLDB_lr>dbi %0,%1,%2,%3"
[(set_attr "type" "vecsimple")])
-(define_insn "xxblend_<mode>"
- [(set (match_operand:VM3 0 "register_operand" "=wa")
- (unspec:VM3 [(match_operand:VM3 1 "register_operand" "wa")
- (match_operand:VM3 2 "register_operand" "wa")
- (match_operand:VM3 3 "register_operand" "wa")]
- UNSPEC_XXBLEND))]
- "TARGET_POWER10"
- "xxblendv<VM3_char> %x0,%x1,%x2,%x3"
- [(set_attr "type" "vecsimple")
- (set_attr "prefixed" "yes")])
-
(define_expand "vstrir_<mode>"
[(set (match_operand:VIshort 0 "altivec_register_operand")
(unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand")]
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 6fcfc9fd2ea..44cd380bfa7 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -271,6 +271,21 @@
;; and Vector Integer Multiply/Divide/Modulo Instructions
(define_mode_iterator VIlong [V2DI V4SI])
+;; Like VM2 in altivec.md, just do char, short, int, long, float and double
+(define_mode_iterator VM3 [V4SI
+ V8HI
+ V16QI
+ V4SF
+ V2DF
+ V2DI])
+
+(define_mode_attr VM3_char [(V2DI "d")
+ (V4SI "w")
+ (V8HI "h")
+ (V16QI "b")
+ (V2DF "d")
+ (V4SF "w")])
+
;; Constants for creating unspecs
(define_c_enum "unspec"
[UNSPEC_VSX_CONCAT
@@ -373,6 +388,7 @@
UNSPEC_XXSPLTI32DX
UNSPEC_XXPERMX
UNSPEC_XXEVAL
+ UNSPEC_XXBLEND
])
(define_int_iterator XVCVBF16 [UNSPEC_VSX_XVCVSPBF16
@@ -6447,3 +6463,15 @@
"xxeval %0,%1,%2,%3,%4"
[(set_attr "type" "vecperm")
(set_attr "prefixed" "yes")])
+
+;; XXBLEND support.
+(define_insn "xxblend_<mode>"
+ [(set (match_operand:VM3 0 "vsx_register_operand" "=wa")
+ (unspec:VM3 [(match_operand:VM3 1 "vsx_register_operand" "wa")
+ (match_operand:VM3 2 "vsx_register_operand" "wa")
+ (match_operand:VM3 3 "vsx_register_operand" "wa")]
+ UNSPEC_XXBLEND))]
+ "TARGET_POWER10"
+ "xxblendv<VM3_char> %x0,%x1,%x2,%x3"
+ [(set_attr "type" "vecperm")
+ (set_attr "prefixed" "yes")])
^ permalink raw reply [flat|nested] 3+ messages in thread
* [gcc(refs/users/meissner/heads/work049)] Move XXBLEND from altivec.md to vsx.md.
@ 2021-04-20 23:07 Michael Meissner
0 siblings, 0 replies; 3+ messages in thread
From: Michael Meissner @ 2021-04-20 23:07 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:7d21ba49201430738f06542bceb65b6447a21d30
commit 7d21ba49201430738f06542bceb65b6447a21d30
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Apr 20 19:07:07 2021 -0400
Move XXBLEND from altivec.md to vsx.md.
This patch moves the XXBLEND support from altivec.md to vsx.md. Given
the instruction support all VSX registers, vsx.md is a more proper place
for this instruction.
In doing the move, I made changes to make it fit into the vsx.md
conventions. I changed the mode iterator from VM3 to VBLEND. I changed
the mode attribute from VM3_char to VBLEND_char.
I also changed the register_operand to the more specific
vsx_register_operand.
I was chatting with Pat Haugen, he said that the insn type should be
"vecperm" and not "vecsimple", so I changed this as well.
gcc/
2021-04-20 Michael Meissner <meissner@linux.ibm.com>
* config/rs6000/altivec.md (UNSPEC_XXBLEND): Move to vsx.md.
(VM3): Move to vsx.md.
(VM3_char): Move to vsx.md.
(xxblend_<mode>): Move to vsx.md.
* config/rs6000/vsx.md (UNSPEC_XXEVAL): Move from altivec.md.
(VM3): Move from altivec.md.
(VM3_char): Move from altivec.md.
(xxblend_<mode>): Move from altivec.md. Use vsx_register_operand
instead of register operand. Change the insn type from vecsimple
to vecperm.
Diff:
---
gcc/config/rs6000/altivec.md | 27 ---------------------------
gcc/config/rs6000/vsx.md | 28 ++++++++++++++++++++++++++++
2 files changed, 28 insertions(+), 27 deletions(-)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index a1ba10b0275..ed79a6b85cd 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -175,7 +175,6 @@
UNSPEC_VSTRIL
UNSPEC_SLDB
UNSPEC_SRDB
- UNSPEC_XXBLEND
])
(define_c_enum "unspecv"
@@ -216,21 +215,6 @@
(KF "FLOAT128_VECTOR_P (KFmode)")
(TF "FLOAT128_VECTOR_P (TFmode)")])
-;; Like VM2, just do char, short, int, long, float and double
-(define_mode_iterator VM3 [V4SI
- V8HI
- V16QI
- V4SF
- V2DF
- V2DI])
-
-(define_mode_attr VM3_char [(V2DI "d")
- (V4SI "w")
- (V8HI "h")
- (V16QI "b")
- (V2DF "d")
- (V4SF "w")])
-
;; Map the Vector convert single precision to double precision for integer
;; versus floating point
(define_mode_attr VS_sxwsp [(V4SI "sxw") (V4SF "sp")])
@@ -815,17 +799,6 @@
"vs<SLDB_lr>dbi %0,%1,%2,%3"
[(set_attr "type" "vecsimple")])
-(define_insn "xxblend_<mode>"
- [(set (match_operand:VM3 0 "register_operand" "=wa")
- (unspec:VM3 [(match_operand:VM3 1 "register_operand" "wa")
- (match_operand:VM3 2 "register_operand" "wa")
- (match_operand:VM3 3 "register_operand" "wa")]
- UNSPEC_XXBLEND))]
- "TARGET_POWER10"
- "xxblendv<VM3_char> %x0,%x1,%x2,%x3"
- [(set_attr "type" "vecsimple")
- (set_attr "prefixed" "yes")])
-
(define_expand "vstrir_<mode>"
[(set (match_operand:VIshort 0 "altivec_register_operand")
(unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand")]
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 0e5fb21d234..cea155a5d28 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -271,6 +271,21 @@
;; and Vector Integer Multiply/Divide/Modulo Instructions
(define_mode_iterator VIlong [V2DI V4SI])
+;; Like VM2 in altivec.md, just do char, short, int, long, float and double
+(define_mode_iterator VM3 [V4SI
+ V8HI
+ V16QI
+ V4SF
+ V2DF
+ V2DI])
+
+(define_mode_attr VM3_char [(V2DI "d")
+ (V4SI "w")
+ (V8HI "h")
+ (V16QI "b")
+ (V2DF "d")
+ (V4SF "w")])
+
;; Constants for creating unspecs
(define_c_enum "unspec"
[UNSPEC_VSX_CONCAT
@@ -374,6 +389,7 @@
UNSPEC_XXSPLTI32DX_CONST
UNSPEC_XXPERMX
UNSPEC_XXEVAL
+ UNSPEC_XXBLEND
])
(define_int_iterator XVCVBF16 [UNSPEC_VSX_XVCVSPBF16
@@ -6522,3 +6538,15 @@
"xxeval %0,%1,%2,%3,%4"
[(set_attr "type" "vecperm")
(set_attr "prefixed" "yes")])
+
+;; XXBLEND support.
+(define_insn "xxblend_<mode>"
+ [(set (match_operand:VM3 0 "vsx_register_operand" "=wa")
+ (unspec:VM3 [(match_operand:VM3 1 "vsx_register_operand" "wa")
+ (match_operand:VM3 2 "vsx_register_operand" "wa")
+ (match_operand:VM3 3 "vsx_register_operand" "wa")]
+ UNSPEC_XXBLEND))]
+ "TARGET_POWER10"
+ "xxblendv<VM3_char> %x0,%x1,%x2,%x3"
+ [(set_attr "type" "vecperm")
+ (set_attr "prefixed" "yes")])
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2021-04-21 21:43 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-04-21 17:00 [gcc(refs/users/meissner/heads/work049)] Move XXBLEND from altivec.md to vsx.md Michael Meissner
-- strict thread matches above, loose matches on Subject: below --
2021-04-21 21:43 Michael Meissner
2021-04-20 23:07 Michael Meissner
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).