[gcc(refs/users/meissner/heads/work049)] Generate XXSPLTI32DX for V4SF/V4SI vectors.

[gcc(refs/users/meissner/heads/work049)] Generate XXSPLTI32DX for V4SF/V4SI vectors.

[Michael Meissner]

https://gcc.gnu.org/g:8c7a4872d14bd53562c167c59e8d95a244b9a39c

commit 8c7a4872d14bd53562c167c59e8d95a244b9a39c
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Apr 21 23:28:01 2021 -0400

    Generate XXSPLTI32DX for V4SF/V4SI vectors.
    
    This patch adds support for V4SF and V4SI vectors where the two even
    elements are the same and the two odd elements are the same, but the even
    and odd elements are different.
    
    gcc/
    2021-04-21  Michael Meissner  <meissner@linux.ibm.com>
    
            * config/rs6000/rs6000.c (xxsplti32dx_constant_p): Add support for
            V4SImode and V4SFmode.
            * config/rs6000/vsx.md (XXSPLTI32DX): Add support for V4SImode and
            V4SFmode.
    
    gcc/testsuite/
    2021-04-21  Michael Meissner  <meissner@linux.ibm.com>
    
            * gcc.target/powerpc/vec-splat-constant-v4sf-2.c: New test.
            * gcc.target/powerpc/vec-splat-constant-v4si-2.c: New test.

Diff:
---
 gcc/config/rs6000/rs6000.c                         | 34 +++++++++++++++++++
 gcc/config/rs6000/vsx.md                           |  2 +-
 .../gcc.target/powerpc/vec-splat-constant-v4sf-2.c | 38 ++++++++++++++++++++++
 .../gcc.target/powerpc/vec-splat-constant-v4si-2.c | 36 ++++++++++++++++++++
 4 files changed, 109 insertions(+), 1 deletion(-)

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index d931388d778..1907dc65dec 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6683,6 +6683,40 @@ xxsplti32dx_constant_p (rtx op,
 	*low_ptr = value & 0xffffffff;
 	return true;
       }
+
+    case E_V4SImode:
+    case E_V4SFmode:
+      {
+	/* For V4SI/V4SF, the XXSPLTI32DX instruction pair can represent vectors
+	   where the two even elements are equal and the two odd elements are
+	   equal.  */
+	if (GET_CODE (op) != CONST_VECTOR)
+	  return false;
+
+	rtx op0 = CONST_VECTOR_ELT (op, 0);
+	if (!rtx_equal_p (op0, CONST_VECTOR_ELT (op, 2)))
+	  return false;
+
+	rtx op1 = CONST_VECTOR_ELT (op, 1);
+	if (!rtx_equal_p (op1, CONST_VECTOR_ELT (op, 3)))
+	  return false;
+
+	if (rtx_equal_p (op0, op1))
+	  return false;
+
+	if (mode == V4SImode)
+	  {
+	    *high_ptr = INTVAL (op0);
+	    *low_ptr = INTVAL (op1);
+	  }
+	else
+	  {
+	    *high_ptr = rs6000_const_f32_to_i32 (op0);
+	    *low_ptr = rs6000_const_f32_to_i32 (op1);
+	  }
+
+	return true;
+      }
     }
 
   return false;
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 0efe77489b6..4d0778f4bd6 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -6349,7 +6349,7 @@
 
 ;; XXSPLTI32DX used to create 64-bit constants or vector constants where the
 ;; even elements match and the odd elements match.
-(define_mode_iterator XXSPLTI32DX [SF DF V2DF V2DI])
+(define_mode_iterator XXSPLTI32DX [SF DF V2DF V2DI V4SI V4SF])
 
 (define_insn_and_split "*xxsplti32dx_<mode>"
   [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa")
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf-2.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf-2.c
new file mode 100644
index 00000000000..d534ca296ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf-2.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
+
+/* Test whether XXSPLTIW and XXSPLTI32DX are generated for V4SF vector
+   constants.  */
+
+vector float
+v4sf_const_1_1_1_1 (void)
+{
+  return (vector float) { 1.0f, 1.0f, 1.0f, 1.0f };	/* XXSPLTIW.  */
+}
+
+vector float
+v4sf_const_1_2_1_2 (void)
+{
+  return (vector float) { 1.0f, 2.0f, 1.0f, 2.0f };	/* 2x XXSPLTI32DX.  */
+}
+
+vector float
+v4sf_const_0_3_0_3 (void)
+{
+						/* XXSPLTISB, XXSPLTI32DX.  */
+  return (vector float) { 0.0f, 3.0f, 0, 3.0f };
+}
+
+vector float
+v4sf_const_4_0_4_0 (void)
+{
+						 /* XXSPLTISB, XXSPLTI32DX.  */
+  return (vector float) { 4.0f, 0.0f, 4.0f, 0.0f };
+}
+
+/* { dg-final { scan-assembler-times {\mxxspltiw\M}     1 } } */
+/* { dg-final { scan-assembler-times {\mxxsplti32dx\M}  4 } } */
+/* { dg-final { scan-assembler-times {\mxxspltib\M}     2 } } */
+/* { dg-final { scan-assembler-not   {\mlxvx?\M}          } } */
+/* { dg-final { scan-assembler-not   {\mplxv\M}           } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si-2.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si-2.c
new file mode 100644
index 00000000000..7f74b260f5e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si-2.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
+
+/* Test whether XXSPLTIW and XXSPLTI32DX are generated for V4SI vector
+   constants.  */
+
+vector int
+v4si_const_126_126_126_126 (void)
+{
+  return (vector int) { 126, 126, 126, 126 };	/* XXSPLTIW.  */
+}
+
+vector int
+v4si_const_200_300_200_300 (void)
+{
+  return (vector int) { 200, 300, 200, 300 };	/* 2x XXSPLTI32DX.  */
+}
+
+vector int
+v4si_const_0_400_0_400 (void)
+{
+  return (vector int) { 0, 400, 0, 400 };	/* XXSPLTISB, XXSPLTI32DX.  */
+}
+
+vector int
+v4si_const_500_m1_500_m1 (void)
+{
+  return (vector int) { 500, -1, 500, -1 };	/* XXSPLTISB, XXSPLTI32DX.  */
+}
+
+/* { dg-final { scan-assembler-times {\mxxspltiw\M}     1 } } */
+/* { dg-final { scan-assembler-times {\mxxsplti32dx\M}  4 } } */
+/* { dg-final { scan-assembler-times {\mxxspltib\M}     2 } } */
+/* { dg-final { scan-assembler-not   {\mlxvx?\M}          } } */
+/* { dg-final { scan-assembler-not   {\mplxv\M}           } } */