[gcc(refs/vendors/redhat/heads/gcc-8-branch)] AArch64: Add Neoverse V1 tuning struct

[gcc(refs/vendors/redhat/heads/gcc-8-branch)] AArch64: Add Neoverse V1 tuning struct

[Jakub Jelinek]

https://gcc.gnu.org/g:cf7df5f67487a7c4ce6c15d409799372488c87e5

commit cf7df5f67487a7c4ce6c15d409799372488c87e5
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Fri Oct 2 15:39:11 2020 +0100

    AArch64: Add Neoverse V1 tuning struct
    
    This GCC 8 patch duplicates the Cortex-A72 tuning struct that's
    currently used for Neoverse V1 and
    AARCH64_EXTRA_TUNE_PREFER_ADVSIMD_AUTOVEC tune flag to prefer Advanced
    SIMD over SVE autovectorisation.
    
    gcc/
            * config/aarch64/aarch64.c (neoversev1_tunings): Define.
            * config/aarch64/aarch64-cores.def (zeus): Use it.
            (neoverse-v1): Likewise.

Diff:
---
 gcc/config/aarch64/aarch64-cores.def |  4 ++--
 gcc/config/aarch64/aarch64.c         | 26 ++++++++++++++++++++++++++
 2 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def
index 6a766bfd7cd..29727fabc2a 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -97,8 +97,8 @@ AARCH64_CORE("saphira",     saphira,    falkor,    8_3A,  AARCH64_FL_FOR_ARCH8_3
 /* ARMv8.4-A Architecture Processors.  */
 
 /* ARM ('A') cores. */
-AARCH64_CORE("zeus", zeus, cortexa57, 8_4A,  AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_SVE | AARCH64_FL_RNG, cortexa72, 0x41, 0xd40, -1)
-AARCH64_CORE("neoverse-v1", neoversev1, cortexa57, 8_4A,  AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_SVE | AARCH64_FL_RNG, cortexa72, 0x41, 0xd40, -1)
+AARCH64_CORE("zeus", zeus, cortexa57, 8_4A,  AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_SVE | AARCH64_FL_RNG, neoversev1, 0x41, 0xd40, -1)
+AARCH64_CORE("neoverse-v1", neoversev1, cortexa57, 8_4A,  AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_SVE | AARCH64_FL_RNG, neoversev1, 0x41, 0xd40, -1)
 
 /* Armv8.5-A Architecture Processors.  */
 AARCH64_CORE("neoverse-n2", neoversen2, cortexa57, 8_4A,  AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_F16 | AARCH64_FL_SVE | AARCH64_FL_RNG, cortexa72, 0x41, 0xd49, -1)
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 6c05a6686c5..3d218b6b951 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -760,6 +760,32 @@ static const struct tune_params cortexa72_tunings =
   &generic_prefetch_tune
 };
 
+static const struct tune_params neoversev1_tunings =
+{
+  &cortexa57_extra_costs,
+  &generic_addrcost_table,
+  &cortexa57_regmove_cost,
+  &cortexa57_vector_cost,
+  &generic_branch_cost,
+  &generic_approx_modes,
+  4, /* memmov_cost  */
+  3, /* issue_rate  */
+  (AARCH64_FUSE_AES_AESMC | AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD
+   | AARCH64_FUSE_MOVK_MOVK), /* fusible_ops  */
+  16,	/* function_align.  */
+  4,	/* jump_align.  */
+  8,	/* loop_align.  */
+  2,	/* int_reassoc_width.  */
+  4,	/* fp_reassoc_width.  */
+  1,	/* vec_reassoc_width.  */
+  2,	/* min_div_recip_mul_sf.  */
+  2,	/* min_div_recip_mul_df.  */
+  0,	/* max_case_values.  */
+  tune_params::AUTOPREFETCHER_WEAK,	/* autoprefetcher_model.  */
+  (AARCH64_EXTRA_TUNE_PREFER_ADVSIMD_AUTOVEC),	/* tune_flags.  */
+  &generic_prefetch_tune
+};
+
 static const struct tune_params cortexa73_tunings =
 {
   &cortexa57_extra_costs,