[gcc(refs/vendors/redhat/heads/gcc-8-branch)] early-remat: Handle sets of multiple candidate regs [PR94605]

[gcc(refs/vendors/redhat/heads/gcc-8-branch)] early-remat: Handle sets of multiple candidate regs [PR94605]

[Jakub Jelinek]

https://gcc.gnu.org/g:b335f2f04600d1bf76fe13675808cd4539f7b161

commit b335f2f04600d1bf76fe13675808cd4539f7b161
Author: Richard Sandiford <richard.sandiford@arm.com>
Date:   Mon Apr 26 09:36:47 2021 +0100

    early-remat: Handle sets of multiple candidate regs [PR94605]
    
    early-remat.c:process_block wasn't handling insns that set multiple
    candidate registers, which led to an assertion failure at the end
    of the main loop.
    
    Instructions that set two pseudos aren't rematerialisation candidates in
    themselves, but we still need to track them if another instruction that
    sets the same register is a rematerialisation candidate.
    
    gcc/
            PR rtl-optimization/94605
            * early-remat.c (early_remat::process_block): Handle insns that
            set multiple candidate registers.
    
    gcc/testsuite/
            PR rtl-optimization/94605
            * gcc.target/aarch64/sve/pr94605.c: New test.
    
    (cherry picked from commit 3c3f12e2a7625c9a2f5d74a47dbacb2fd1ae5643)

Diff:
---
 gcc/early-remat.c                              |  2 +-
 gcc/testsuite/gcc.target/aarch64/sve/pr94605.c | 12 ++++++++++++
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/gcc/early-remat.c b/gcc/early-remat.c
index 28eb9b4b2de..bba2c1a6db5 100644
--- a/gcc/early-remat.c
+++ b/gcc/early-remat.c
@@ -1995,7 +1995,7 @@ early_remat::process_block (basic_block bb)
 	}
 
       /* Now process definitions.  */
-      if (next_def && insn == next_def->insn)
+      while (next_def && insn == next_def->insn)
 	{
 	  unsigned int gen = canon_candidate (next_candidate);
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr94605.c b/gcc/testsuite/gcc.target/aarch64/sve/pr94605.c
new file mode 100644
index 00000000000..593e959e292
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pr94605.c
@@ -0,0 +1,12 @@
+/* { dg-options "-O2 -msve-vector-bits=256" } */
+
+typedef int v8si __attribute__((vector_size(32)));
+int g (v8si, v8si);
+
+void
+f (void)
+{
+  v8si x = {}, y = {};
+  while (g (x, y))
+    asm ("" : "+w" (x), "+w" (y));
+}