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From: Michael Meissner <meissner@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/meissner/heads/work053)] Revert patches
Date: Tue, 18 May 2021 01:28:29 +0000 (GMT) [thread overview]
Message-ID: <20210518012829.187E93857817@sourceware.org> (raw)
https://gcc.gnu.org/g:e226978b94be055843b07130a389992984784856
commit e226978b94be055843b07130a389992984784856
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon May 17 21:26:59 2021 -0400
Revert patches
gcc/
2021-05-17 Michael Meissner <meissner@linux.ibm.com>
Revert patch
* config/rs6000/rs6000.c (rs6000_maybe_emit_fp_cmove): Add IEEE
128-bit floating point conditional move support.
(have_compare_and_set_mask): Add IEEE 128-bit floating point
types.
* config/rs6000/rs6000.md (mov<mode>cc, IEEE128 iterator): New insn.
(mov<mode>cc_p10, IEEE128 iterator): New insn.
(mov<mode>cc_invert_p10, IEEE128 iterator): New insn.
(fpmask<mode>, IEEE128 iterator): New insn.
(xxsel<mode>, IEEE128 iterator): New insn.
gcc/testsuite/
2021-05-17 Michael Meissner <meissner@linux.ibm.com>
Revert patch
* gcc.target/powerpc/float128-cmove.c: New test.
* gcc.target/powerpc/float128-minmax-3.c: New test.
gcc/
2021-05-17 Michael Meissner <meissner@linux.ibm.com>
Revert patch
* config/rs6000/rs6000.c (rs6000_emit_minmax): Add support for ISA
3.1 IEEE 128-bit floating point xsmaxcqp and xsmincqp
instructions.
* config/rs6000/rs6000.md (s<minmax><mode>3, IEEE128 iterator):
New insns.
gcc/testsuite/
2021-05-17 Michael Meissner <meissner@linux.ibm.com>
Revert patch
* gcc.target/powerpc/float128-minmax-2.c: New test.
Diff:
---
gcc/config/rs6000/rs6000.c | 41 +-------
gcc/config/rs6000/rs6000.md | 117 ---------------------
gcc/testsuite/gcc.target/powerpc/float128-cmove.c | 58 ----------
.../gcc.target/powerpc/float128-minmax-2.c | 15 ---
.../gcc.target/powerpc/float128-minmax-3.c | 15 ---
5 files changed, 3 insertions(+), 243 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index ef1ebaaee05..0d0595dddd6 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -15706,8 +15706,8 @@ rs6000_emit_vector_cond_expr (rtx dest, rtx op_true, rtx op_false,
return 1;
}
-/* Possibly emit the xsmaxc{dp,qp} and xsminc{dp,qp} instructions to emit a
- maximum or minimum with "C" semantics.
+/* Possibly emit the xsmaxcdp and xsmincdp instructions to emit a maximum or
+ minimum with "C" semantics.
Unless you use -ffast-math, you can't use these instructions to replace
conditions that implicitly reverse the condition because the comparison
@@ -15783,7 +15783,6 @@ rs6000_maybe_emit_fp_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
enum rtx_code code = GET_CODE (op);
rtx op0 = XEXP (op, 0);
rtx op1 = XEXP (op, 1);
- machine_mode compare_mode = GET_MODE (op0);
machine_mode result_mode = GET_MODE (dest);
rtx compare_rtx;
rtx cmove_rtx;
@@ -15792,35 +15791,6 @@ rs6000_maybe_emit_fp_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
if (!can_create_pseudo_p ())
return 0;
- /* We allow the comparison to be either SFmode/DFmode and the true/false
- condition to be either SFmode/DFmode. I.e. we allow:
-
- float a, b;
- double c, d, r;
-
- r = (a == b) ? c : d;
-
- and:
-
- double a, b;
- float c, d, r;
-
- r = (a == b) ? c : d;
-
- but we don't allow intermixing the IEEE 128-bit floating point types with
- the 32/64-bit scalar types.
-
- It gets too messy where SFmode/DFmode can use any register and TFmode/KFmode
- can only use Altivec registers. In addtion, we would need to do a XXPERMDI
- if we compare SFmode/DFmode and move TFmode/KFmode. */
-
- if (compare_mode == result_mode
- || (compare_mode == SFmode && result_mode == DFmode)
- || (compare_mode == DFmode && result_mode == SFmode))
- ;
- else
- return false;
-
switch (code)
{
case EQ:
@@ -15873,10 +15843,6 @@ have_compare_and_set_mask (machine_mode mode)
case E_DFmode:
return TARGET_P9_MINMAX;
- case E_KFmode:
- case E_TFmode:
- return TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode);
-
default:
break;
}
@@ -16145,8 +16111,7 @@ rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
/* VSX/altivec have direct min/max insns. */
if ((code == SMAX || code == SMIN)
&& (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
- || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))
- || (TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode))))
+ || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
{
emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1)));
return;
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 0c76338c734..0bfeb24d9e8 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5196,17 +5196,6 @@
}
[(set_attr "type" "fp")])
-;; Min/max for ISA 3.1 IEEE 128-bit floating point
-(define_insn "s<minmax><mode>3"
- [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
- (fp_minmax:IEEE128
- (match_operand:IEEE128 1 "altivec_register_operand" "v")
- (match_operand:IEEE128 2 "altivec_register_operand" "v")))]
- "TARGET_POWER10"
- "xs<minmax>cqp %0,%1,%2"
- [(set_attr "type" "vecfloat")
- (set_attr "size" "128")])
-
;; The conditional move instructions allow us to perform max and min operations
;; even when we don't have the appropriate max/min instruction using the FSEL
;; instruction.
@@ -5431,112 +5420,6 @@
"xxsel %x0,%x4,%x3,%x1"
[(set_attr "type" "vecmove")])
-;; Support for ISA 3.1 IEEE 128-bit conditional move. The mode used in the
-;; comparison must be the same as used in the conditional move.
-(define_expand "mov<mode>cc"
- [(set (match_operand:IEEE128 0 "gpc_reg_operand")
- (if_then_else:IEEE128 (match_operand 1 "comparison_operator")
- (match_operand:IEEE128 2 "gpc_reg_operand")
- (match_operand:IEEE128 3 "gpc_reg_operand")))]
- "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
-{
- if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
- DONE;
- else
- FAIL;
-})
-
-(define_insn_and_split "*mov<mode>cc_p10"
- [(set (match_operand:IEEE128 0 "altivec_register_operand" "=&v,v")
- (if_then_else:IEEE128
- (match_operator:CCFP 1 "fpmask_comparison_operator"
- [(match_operand:IEEE128 2 "altivec_register_operand" "v,v")
- (match_operand:IEEE128 3 "altivec_register_operand" "v,v")])
- (match_operand:IEEE128 4 "altivec_register_operand" "v,v")
- (match_operand:IEEE128 5 "altivec_register_operand" "v,v")))
- (clobber (match_scratch:V2DI 6 "=0,&v"))]
- "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
- "#"
- "&& 1"
- [(set (match_dup 6)
- (if_then_else:V2DI (match_dup 1)
- (match_dup 7)
- (match_dup 8)))
- (set (match_dup 0)
- (if_then_else:IEEE128 (ne (match_dup 6)
- (match_dup 8))
- (match_dup 4)
- (match_dup 5)))]
-{
- if (GET_CODE (operands[6]) == SCRATCH)
- operands[6] = gen_reg_rtx (V2DImode);
-
- operands[7] = CONSTM1_RTX (V2DImode);
- operands[8] = CONST0_RTX (V2DImode);
-}
- [(set_attr "length" "8")
- (set_attr "type" "vecperm")])
-
-;; Handle inverting the fpmask comparisons.
-(define_insn_and_split "*mov<mode>cc_invert_p10"
- [(set (match_operand:IEEE128 0 "altivec_register_operand" "=&v,v")
- (if_then_else:IEEE128
- (match_operator:CCFP 1 "invert_fpmask_comparison_operator"
- [(match_operand:IEEE128 2 "altivec_register_operand" "v,v")
- (match_operand:IEEE128 3 "altivec_register_operand" "v,v")])
- (match_operand:IEEE128 4 "altivec_register_operand" "v,v")
- (match_operand:IEEE128 5 "altivec_register_operand" "v,v")))
- (clobber (match_scratch:V2DI 6 "=0,&v"))]
- "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
- "#"
- "&& 1"
- [(set (match_dup 6)
- (if_then_else:V2DI (match_dup 9)
- (match_dup 7)
- (match_dup 8)))
- (set (match_dup 0)
- (if_then_else:IEEE128 (ne (match_dup 6)
- (match_dup 8))
- (match_dup 5)
- (match_dup 4)))]
-{
- rtx op1 = operands[1];
- enum rtx_code cond = reverse_condition_maybe_unordered (GET_CODE (op1));
-
- if (GET_CODE (operands[6]) == SCRATCH)
- operands[6] = gen_reg_rtx (V2DImode);
-
- operands[7] = CONSTM1_RTX (V2DImode);
- operands[8] = CONST0_RTX (V2DImode);
-
- operands[9] = gen_rtx_fmt_ee (cond, CCFPmode, operands[2], operands[3]);
-}
- [(set_attr "length" "8")
- (set_attr "type" "vecperm")])
-
-(define_insn "*fpmask<mode>"
- [(set (match_operand:V2DI 0 "altivec_register_operand" "=v")
- (if_then_else:V2DI
- (match_operator:CCFP 1 "fpmask_comparison_operator"
- [(match_operand:IEEE128 2 "altivec_register_operand" "v")
- (match_operand:IEEE128 3 "altivec_register_operand" "v")])
- (match_operand:V2DI 4 "all_ones_constant" "")
- (match_operand:V2DI 5 "zero_constant" "")))]
- "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
- "xscmp%V1qp %0,%2,%3"
- [(set_attr "type" "fpcompare")])
-
-(define_insn "*xxsel<mode>"
- [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
- (if_then_else:IEEE128
- (ne (match_operand:V2DI 1 "altivec_register_operand" "v")
- (match_operand:V2DI 2 "zero_constant" ""))
- (match_operand:IEEE128 3 "altivec_register_operand" "v")
- (match_operand:IEEE128 4 "altivec_register_operand" "v")))]
- "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
- "xxsel %x0,%x4,%x3,%x1"
- [(set_attr "type" "vecmove")])
-
\f
;; Conversions to and from floating-point.
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-cmove.c b/gcc/testsuite/gcc.target/powerpc/float128-cmove.c
deleted file mode 100644
index 2fae8dc23bc..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/float128-cmove.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target ppc_float128_hw } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#ifndef TYPE
-#ifdef __LONG_DOUBLE_IEEE128__
-#define TYPE long double
-
-#else
-#define TYPE _Float128
-#endif
-#endif
-
-/* Verify that the ISA 3.1 (power10) IEEE 128-bit conditional move instructions
- are generated. */
-
-TYPE
-eq (TYPE a, TYPE b, TYPE c, TYPE d)
-{
- return (a == b) ? c : d;
-}
-
-TYPE
-ne (TYPE a, TYPE b, TYPE c, TYPE d)
-{
- return (a != b) ? c : d;
-}
-
-TYPE
-lt (TYPE a, TYPE b, TYPE c, TYPE d)
-{
- return (a < b) ? c : d;
-}
-
-TYPE
-le (TYPE a, TYPE b, TYPE c, TYPE d)
-{
- return (a <= b) ? c : d;
-}
-
-TYPE
-gt (TYPE a, TYPE b, TYPE c, TYPE d)
-{
- return (a > b) ? c : d;
-}
-
-TYPE
-ge (TYPE a, TYPE b, TYPE c, TYPE d)
-{
- return (a >= b) ? c : d;
-}
-
-/* { dg-final { scan-assembler-times {\mxscmpeqqp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mxscmpgeqp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mxscmpgtqp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mxxsel\M} 6 } } */
-/* { dg-final { scan-assembler-not {\mxscmpuqp\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c b/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c
deleted file mode 100644
index c71ba08c9f8..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/* { dg-require-effective-target ppc_float128_hw } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -ffast-math" } */
-
-#ifndef TYPE
-#define TYPE _Float128
-#endif
-
-/* Test that the fminf128/fmaxf128 functions generate if/then/else and not a
- call. */
-TYPE f128_min (TYPE a, TYPE b) { return __builtin_fminf128 (a, b); }
-TYPE f128_max (TYPE a, TYPE b) { return __builtin_fmaxf128 (a, b); }
-
-/* { dg-final { scan-assembler {\mxsmaxcqp\M} } } */
-/* { dg-final { scan-assembler {\mxsmincqp\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-minmax-3.c b/gcc/testsuite/gcc.target/powerpc/float128-minmax-3.c
deleted file mode 100644
index 6f7627c0f2a..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/float128-minmax-3.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/* { dg-require-effective-target ppc_float128_hw } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#ifndef TYPE
-#define TYPE _Float128
-#endif
-
-/* Test that the fminf128/fmaxf128 functions generate if/then/else and not a
- call. */
-TYPE f128_min (TYPE a, TYPE b) { return (a < b) ? a : b; }
-TYPE f128_max (TYPE a, TYPE b) { return (b > a) ? b : a; }
-
-/* { dg-final { scan-assembler {\mxsmaxcqp\M} } } */
-/* { dg-final { scan-assembler {\mxsmincqp\M} } } */
next reply other threads:[~2021-05-18 1:28 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-18 1:28 Michael Meissner [this message]
2021-05-18 16:07 Michael Meissner
2021-05-19 14:19 Michael Meissner
2021-05-20 12:31 Michael Meissner
2021-05-25 5:14 Michael Meissner
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