public inbox for gcc-cvs@sourceware.org
help / color / mirror / Atom feed
From: Michael Meissner <meissner@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/meissner/heads/work053)] Revert patches.
Date: Thu, 20 May 2021 12:31:54 +0000 (GMT) [thread overview]
Message-ID: <20210520123154.6B3D63848032@sourceware.org> (raw)
https://gcc.gnu.org/g:ea543e401fafab119e97e82d0d02dadfca3a8dc0
commit ea543e401fafab119e97e82d0d02dadfca3a8dc0
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu May 20 08:30:09 2021 -0400
Revert patches.
gcc/
2021-05-19 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* config/rs6000/constraint.md (eD): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): If the constant
can be loaded with XXSPLTI32DX, it is easy.
(xxsplti32dx_operand): New predicate.
(easy_vector_constant): If the constant can be loaded with
XXSPLTI32DX, it is easy.
* config/rs6000/rs6000-protos.h (xxsplti32dx_constant_p): New
declaration.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
support for -mxxsplti32dx.
(xxsplti32dx_constant_float_p): New helper function.
(xxsplti32dx_constant_p): New function.
(output_vec_const_move): If the operand can be loaded with
XXSPLTI32DX, split it.
(rs6000_opt_masks): Add -mxxsplti32dx.
* config/rs6000/rs6000.md (movsf_hardfloat): Add support for
constants loaded with XXSPLTI32DX.
(mov<mode>_hardfloat32, FMOVE64 iterator): Add support for
constants loaded with XXSPLTI32DX.
(mov<mode>_hardfloat64, FMOVE64 iterator): Add support for
constants loaded with XXSPLTI32DX.
* config/rs6000/rs6000.opt (-mxxsplti32dx): New option.
* config/rs6000/vsx.md (UNSPEC_XXSPLTI32DX_CONST): New unspec.
(XXSPLTI32DX): New mode iterator.
(xxsplti32dx_<mode>): New insn and splitter for XXSPLTI32DX.
(xxsplti32dx_<mode>_first): New insn.
(xxsplti32dx_<mode>_second): New insn.
gcc/testsuite/
2021-05-19 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* gcc.target/powerpc/vec-splat-constant-sf.c: Update insn count.
* gcc.target/powerpc/vec-splat-constant-df.c: Update insn count.
* gcc.target/powerpc/vec-splat-constant-v2df.c: Update insn
count.
gcc/
2021-05-19 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* config/rs6000/constraints.md (eF): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): If we can load
the scalar constant with XXSPLTIDP, the floating point constant is
easy.
(xxspltidp_operand): New predicate.
(easy_vector_constant): If we can generate XXSPLTIDP, mark the
vector constant as easy.
* config/rs6000/rs6000-cpus.def (OTHER_POWER10_MASKS): Add
-mxxspltidp support.
(POWERPC_MASKS): Add -mxxspltidp support.
* config/rs6000/rs6000-protos.h (xxspltidp_constant_p): New
declaration.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
-mxxspltidp support.
(const_vector_element_all_same): New function.
(xxspltidp_constant_p): New function.
(output_vec_const_move): Add support for XXSPLTIDP.
(rs6000_opt_masks): Add -mxxspltidp support.
(rs6000_emit_xxspltidp_v2df): Change function to implement the
XXSPLTIDP instruction.
* config/rs6000/rs6000.md (movsf_hardfloat): Add XXSPLTIDP
support.
(mov<mode>_hardfloat32, FMOVE64 iterator): Add XXSPLTIDP support.
(mov<mode>_hardfloat64, FMOVE64 iterator): Add XXSPLTIDP support.
* config/rs6000/rs6000.opt (-mxxspltidp): New switch.
* config/rs6000/vsx.md (UNSPEC_XXSPLTIDP): Rename UNSPEC_XXSPLTID
to UNSPEC_XXSPLTIDP to match the instruction.
(xxspltidp_v2df): Use 'use' for the expand arguments, instead of
writing out an insn.
(xxspltidp_v2df_inst): Delete.
(XXSPLTIDP): New mode iterator.
(xxspltidp_<mode>_internal1): New define_insn_and_split.
(xxspltidp_<mode>_internal2): New define_insn.
gcc/testsuite/
2021-05-19 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* gcc.target/powerpc/vec-splat-constant-sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-df.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2df.c: New test.
gcc/
2021-05-19 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* config/rs6000/predicates.md (xxspltiw_operand): New predicate.
(easy_vector_constant): If we can use XXSPLTIW, the vector
constant is easy.
* config/rs6000/rs6000-cpus.def (ISA_3_1_MASKS_SERVER): Add
-mxxspltiw support.
(POWERPC_MASKS): Add -mxxspltiw support.
* config/rs6000/rs6000-protos.h (sign_extend_mode_constant): New
declaration.
(zero_extend_mode_constant); New declaration.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
-mxxspltiw support.
(xxspltib_constant_p): If we can generate XXSPLTIW, don't generate
a XXSPLTIB and an extend instruction.
(output_vec_const_move): Add support for loading up vector
constants with XXSPLTIW.
(rs6000_opt_masks): Add -mxxspltiw.
(sign_extend_mode_constant): New function.
(zero_extend_mode_constant): New function.
* config/rs6000/rs6000.opt (-mxxspltiw): New debug switch.
* config/rs6000/vsx.md (UNSPEC_XXSPLTIW): Delete.
(xxspltiw_v8hi): New insn.
(xxspltiw_v4si): Rewrite to generate a vector constant.
(xxspltiw_v4sf): Rewrite to generate a vector constant.
(xxspltiw_v4si_inst): Delete.
(xxspltiw_v4sf_inst): Delete.
(xxspltiw_v8hi_dup): New insn.
(xxspltiw_v4si_dup): New insn.
(xxspltiw_v4sf_dup): New insn.
(XXSPLTIW): New mode iterator.
(XXSPLTIW splitter): New insn splitter for XXSPLTIW.
gcc/testsuite/
2021-05-19 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* gcc.target/powerpc/pr86731-fwrapv.c: Turn off power10 code
generation.
* gcc.target/powerpc/vec-splati-runnable.c: Update insn counts.
* gcc.target/powerpc/vec-splat-constant-v4sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4si.c: New test.
* gcc.target/powerpc/vec-splat-constant-v8hi.c: New test.
Diff:
---
gcc/config/rs6000/constraints.md | 11 -
gcc/config/rs6000/predicates.md | 68 -----
gcc/config/rs6000/rs6000-cpus.def | 9 +-
gcc/config/rs6000/rs6000-protos.h | 6 -
gcc/config/rs6000/rs6000.c | 298 +--------------------
gcc/config/rs6000/rs6000.md | 81 ++----
gcc/config/rs6000/rs6000.opt | 12 -
gcc/config/rs6000/vsx.md | 275 +++----------------
gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv.c | 7 -
.../gcc.target/powerpc/vec-splat-constant-df.c | 63 -----
.../gcc.target/powerpc/vec-splat-constant-sf.c | 63 -----
.../gcc.target/powerpc/vec-splat-constant-v2df.c | 66 -----
.../gcc.target/powerpc/vec-splat-constant-v4sf.c | 66 -----
.../gcc.target/powerpc/vec-splat-constant-v4si.c | 51 ----
.../gcc.target/powerpc/vec-splat-constant-v8hi.c | 53 ----
.../gcc.target/powerpc/vec-splati-runnable.c | 4 +-
16 files changed, 72 insertions(+), 1061 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index d665e2a94db..561ce9797af 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -208,17 +208,6 @@
(and (match_code "const_int")
(match_test "((- (unsigned HOST_WIDE_INT) ival) + 0x8000) < 0x10000")))
-;; SF/DF/V2DF/DI/V2DI scalar or vector constant that can be loaded with a pair
-;; of XXSPLTI32DX instructions.
-(define_constraint "eD"
- "A vector constant that can be loaded with XXSPLTI32DX instructions."
- (match_operand 0 "xxsplti32dx_operand"))
-
-;; SF/DF/V2DF scalar or vector constant that can be loaded with XXSPLTIDP
-(define_constraint "eF"
- "A vector constant that can be loaded with the XXSPLTIDP instruction."
- (match_operand 0 "xxspltidp_operand"))
-
;; 34-bit signed integer constant
(define_constraint "eI"
"A signed 34-bit integer constant if prefixed instructions are supported."
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index fc30b69018d..e21bc745f72 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -601,16 +601,6 @@
if (TARGET_VSX && op == CONST0_RTX (mode))
return 1;
- /* If we have the ISA 3.1 XXSPLTIDP instruction, see if the constant can
- be loaded with that instruction. */
- if (xxspltidp_operand (op, mode))
- return 1;
-
- /* If we have the ISA 3.1 XXSPLTI32DX instruction, see if the constant can
- be loaded with a pair of those instructions. */
- if (xxsplti32dx_operand (op, mode))
- return 1;
-
/* Otherwise consider floating point constants hard, so that the
constant gets pushed to memory during the early RTL phases. This
has the advantage that double precision constants that can be
@@ -650,55 +640,6 @@
return num_insns == 1;
})
-;; Return 1 if the operand is a CONST_VECTOR that can be loaded with the
-;; XXSPLTIW instruction. Do not return 1 if the constant can be generated with
-;; XXSPLTIB or VSPLTIS{H,W}
-(define_predicate "xxspltiw_operand"
- (match_code "const_vector")
-{
- if (!TARGET_XXSPLTIW)
- return false;
-
- if (mode != V8HImode && mode != V4SImode && mode != V4SFmode)
- return false;
-
- rtx element = CONST_VECTOR_ELT (op, 0);
- for (size_t i = 1; i < GET_MODE_NUNITS (mode); i++)
- if (!rtx_equal_p (element, CONST_VECTOR_ELT (op, i)))
- return false;
-
- if (element == CONST0_RTX (GET_MODE_INNER (mode)))
- return false;
-
- if (CONST_INT_P (element) && EASY_VECTOR_15 (INTVAL (element)))
- return false;
-
- return true;
-})
-
-;; Return 1 if operand is a SF/DF CONST_DOUBLE or V2DF CONST_VECTOR that can be
-;; loaded via the ISA 3.1 XXSPLTIDP instruction. Do not return true if the
-;; value is 0.0, since that is easy to generate without using XXSPLTIDP.
-(define_predicate "xxspltidp_operand"
- (match_code "const_double,const_vector,vec_duplicate")
-{
- if (op == CONST0_RTX (mode))
- return false;
-
- HOST_WIDE_INT value = 0;
- return xxspltidp_constant_p (op, mode, &value);
-})
-
-;; Return 1 if operand is a SF/DF CONST_DOUBLE or V2DF CONST_VECTOR that can be
-;; loaded via a pair f ISA 3.1 XXSPLTI32DX instructions. Do not return true if
-;; the value can be loaded with the XXSPLTIDP instruction or XXSPLTIB to load 0.
-(define_predicate "xxsplti32dx_operand"
- (match_code "const_double,const_vector,vec_duplicate")
-{
- HOST_WIDE_INT high = 0, low = 0;
- return xxsplti32dx_constant_p (op, mode, &high, &low);
-})
-
;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
;; vector register without using memory.
(define_predicate "easy_vector_constant"
@@ -712,15 +653,6 @@
if (zero_constant (op, mode) || all_ones_constant (op, mode))
return true;
- if (xxspltiw_operand (op, mode))
- return true;
-
- if (xxspltidp_operand (op, mode))
- return true;
-
- if (xxsplti32dx_operand (op, mode))
- return true;
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (op, mode, &num_insns, &value))
return true;
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index 3b657e490b1..cbbb42c1b3a 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -85,9 +85,7 @@
| OTHER_POWER10_MASKS \
| OPTION_MASK_P10_FUSION \
| OPTION_MASK_P10_FUSION_LD_CMPI \
- | OPTION_MASK_P10_FUSION_2LOGICAL \
- | OPTION_MASK_XXSPLTIDP \
- | OPTION_MASK_XXSPLTIW)
+ | OPTION_MASK_P10_FUSION_2LOGICAL)
/* Flags that need to be turned off if -mno-power9-vector. */
#define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \
@@ -162,9 +160,8 @@
| OPTION_MASK_RECIP_PRECISION \
| OPTION_MASK_SOFT_FLOAT \
| OPTION_MASK_STRICT_ALIGN_OPTIONAL \
- | OPTION_MASK_VSX \
- | OPTION_MASK_XXSPLTIDP \
- | OPTION_MASK_XXSPLTIW)
+ | OPTION_MASK_VSX)
+
#endif
/* This table occasionally claims that a processor does not support a
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 286f79143ef..c407034d58c 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -32,9 +32,6 @@ extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, int, int, int,
extern bool easy_altivec_constant (rtx, machine_mode);
extern bool xxspltib_constant_p (rtx, machine_mode, int *, int *);
-extern bool xxspltidp_constant_p (rtx, machine_mode, HOST_WIDE_INT *);
-extern bool xxsplti32dx_constant_p (rtx, machine_mode, HOST_WIDE_INT *,
- HOST_WIDE_INT *);
extern int vspltis_shifted (rtx);
extern HOST_WIDE_INT const_vector_elt_as_int (rtx, unsigned int);
extern bool macho_lo_sum_memory_operand (rtx, machine_mode);
@@ -286,9 +283,6 @@ extern void rs6000_asm_output_dwarf_pcrel (FILE *file, int size,
extern void rs6000_asm_output_dwarf_datarel (FILE *file, int size,
const char *label);
extern long rs6000_const_f32_to_i32 (rtx operand);
-extern HOST_WIDE_INT sign_extend_mode_constant (machine_mode, HOST_WIDE_INT);
-extern unsigned HOST_WIDE_INT zero_extend_mode_constant (machine_mode,
- HOST_WIDE_INT);
/* Declare functions in rs6000-c.c */
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 59660bda5f1..ef1ebaaee05 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -4487,22 +4487,6 @@ rs6000_option_override_internal (bool global_init_p)
if (!TARGET_PCREL && TARGET_PCREL_OPT)
rs6000_isa_flags &= ~OPTION_MASK_PCREL_OPT;
- if (TARGET_POWER10 && TARGET_VSX)
- {
- if ((rs6000_isa_flags_explicit & OPTION_MASK_XXSPLTI32DX) == 0)
- rs6000_isa_flags |= OPTION_MASK_XXSPLTI32DX;
-
- if ((rs6000_isa_flags_explicit & OPTION_MASK_XXSPLTIW) == 0)
- rs6000_isa_flags |= OPTION_MASK_XXSPLTIW;
-
- if ((rs6000_isa_flags_explicit & OPTION_MASK_XXSPLTIDP) == 0)
- rs6000_isa_flags |= OPTION_MASK_XXSPLTIDP;
- }
- else
- rs6000_isa_flags &= ~(OPTION_MASK_XXSPLTIW
- | OPTION_MASK_XXSPLTIDP
- | OPTION_MASK_XXSPLTI32DX);
-
if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags);
@@ -6480,11 +6464,9 @@ xxspltib_constant_p (rtx op,
/* See if we could generate vspltisw/vspltish directly instead of xxspltib +
sign extend. Special case 0/-1 to allow getting any VSX register instead
- of an Altivec register. Also if we can generate a XXSPLTIW instruction,
- don't emit a XXSPLTIB and an extend instruction. */
- if ((mode == V4SImode || mode == V8HImode)
- && !IN_RANGE (value, -1, 0)
- && (EASY_VECTOR_15 (value) || TARGET_XXSPLTIW))
+ of an Altivec register. */
+ if ((mode == V4SImode || mode == V8HImode) && !IN_RANGE (value, -1, 0)
+ && EASY_VECTOR_15 (value))
return false;
/* Return # of instructions and the constant byte for XXSPLTIB. */
@@ -6501,209 +6483,6 @@ xxspltib_constant_p (rtx op,
return true;
}
-/* Return the element of a constant vector whose elements are all the same. In
- addition if VEC_DUPLICATE is used, return the element being duplicated. If
- neither is true, return NULL_RTX. */
-
-static rtx
-const_vector_element_all_same (rtx op)
-{
- if (GET_CODE (op) == VEC_DUPLICATE)
- {
- rtx element = XEXP (op, 0);
- return (CONST_INT_P (element) || CONST_DOUBLE_P (element)
- ? element
- : NULL_RTX);
- }
-
- else if (GET_CODE (op) == CONST_VECTOR)
- {
- machine_mode mode = GET_MODE (op);
- size_t n_elts = GET_MODE_NUNITS (mode);
- rtx element = CONST_VECTOR_ELT (op, 0);
-
- for (size_t i = 1; i < n_elts; i++)
- if (!rtx_equal_p (element, CONST_VECTOR_ELT (op, 1)))
- return NULL_RTX;
-
- return element;
- }
-
- return NULL_RTX;
-}
-
-/* Return true if OP is of the given MODE and can be synthesized with ISA 3.1
- XXSPLTIDP instruction.
-
- Return the constant that is being split via CONSTANT_PTR to use in the
- XXSPLTIDP instruction. */
-
-bool
-xxspltidp_constant_p (rtx op,
- machine_mode mode,
- HOST_WIDE_INT *constant_ptr)
-{
- *constant_ptr = 0;
-
- if (!TARGET_XXSPLTIDP)
- return false;
-
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- rtx element = op;
- if (mode == V2DFmode)
- {
- element = const_vector_element_all_same (op);
- if (!element)
- return false;
-
- mode = DFmode;
- }
-
- if (mode != SFmode && mode != DFmode)
- return false;
-
- if (GET_MODE (element) != mode)
- return false;
-
- if (!CONST_DOUBLE_P (element))
- return false;
-
- /* Don't return true for 0.0 since that is easy to create without
- XXSPLTIDP. */
- if (element == CONST0_RTX (mode))
- return false;
-
- /* If the value doesn't fit in a SFmode, exactly, we can't use XXSPLTIDP. */
- const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (element);
- if (!exact_real_truncate (SFmode, rv))
- return 0;
-
- long value;
- REAL_VALUE_TO_TARGET_SINGLE (*rv, value);
-
- /* Test for SFmode denormal (exponent is 0, mantissa field is non-zero). */
- if (((value & 0x7F800000) == 0) && ((value & 0x7FFFFF) != 0))
- return false;
-
- *constant_ptr = value;
- return true;
-}
-
-/* Return true if OP is a floating point constant that can be loaded with the
- XXSPLTI32DX instruction. If the constant can be loaded with the simpler
- XXSPLTIDP (constants that can fit as SFmode constants) or XXSPLTIB (0.0)
- instructions, return false.
-
- Return the two 32-bit constants to use in the two XXSPLTI32DX instructions
- via HIGH_PTR and LOW_PTR. */
-
-static bool
-xxsplti32dx_constant_float_p (rtx op,
- machine_mode mode,
- HOST_WIDE_INT *high_ptr,
- HOST_WIDE_INT *low_ptr)
-{
- HOST_WIDE_INT xxspltidp_value = 0;
-
- if (!CONST_DOUBLE_P (op))
- return false;
-
- if (mode != SFmode && mode != DFmode)
- return false;
-
- if (op == CONST0_RTX (mode))
- return false;
-
- if (xxspltidp_constant_p (op, mode, &xxspltidp_value))
- return false;
-
- long high_low[2];
- const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (op);
- REAL_VALUE_TO_TARGET_DOUBLE (*rv, high_low);
-
- /* The double precision value is laid out in memory order. We need to undo
- this for XXSPLTI32DX. */
- if (!BYTES_BIG_ENDIAN)
- std::swap (high_low[0], high_low[1]);
-
- *high_ptr = high_low[0];
- *low_ptr = high_low[1];
- return true;
-}
-
-/* Return true if OP is of the given MODE and can be synthesized with ISA 3.1
- XXSPLTI32DX instruction. If the instruction can be synthesized with
- XXSPLTIDP or is 0/-1, return false.
-
- We handle the following types of constants:
-
- 1) vector double constants where each element is the same and you can't
- load the constant with XXSPLTIDP;
-
- 2) vector long long constants where each element is the same;
-
- 3) Scalar floating point constants that can't be loaded with XXSPLTIDP.
-
- Return the two 32-bit constants to use in the two XXSPLTI32DX instructions
- via HIGH_PTR and LOW_PTR. */
-
-bool
-xxsplti32dx_constant_p (rtx op,
- machine_mode mode,
- HOST_WIDE_INT *high_ptr,
- HOST_WIDE_INT *low_ptr)
-{
- *high_ptr = *low_ptr = 0;
-
- if (!TARGET_XXSPLTI32DX)
- return false;
-
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- if (op == CONST0_RTX (mode))
- return false;
-
- switch (mode)
- {
- default:
- break;
-
- case E_V2DFmode:
- {
- rtx ele = const_vector_element_all_same (op);
- if (!ele)
- return false;
-
- return xxsplti32dx_constant_float_p (ele, DFmode, high_ptr, low_ptr);
- }
-
- case E_SFmode:
- case E_DFmode:
- return xxsplti32dx_constant_float_p (op, mode, high_ptr, low_ptr);
-
- case E_V2DImode:
- {
- rtx ele = const_vector_element_all_same (op);
- if (!ele)
- return false;
-
- /* If we can generate XXSPLTIB and VEXTSB2D, don't return true. */
- HOST_WIDE_INT value = INTVAL (ele);
- if (IN_RANGE (value, -128, 127))
- return false;
-
- *high_ptr = value >> 32;
- *low_ptr = value & 0xffffffff;
- return true;
- }
- }
-
- return false;
-}
-
const char *
output_vec_const_move (rtx *operands)
{
@@ -6748,13 +6527,6 @@ output_vec_const_move (rtx *operands)
gcc_unreachable ();
}
- if (xxspltiw_operand (vec, mode)
- || xxspltidp_operand (vec, mode))
- return "#";
-
- if (xxsplti32dx_operand (vec, mode))
- return "#";
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
{
@@ -24346,9 +24118,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "string", 0, false, true },
{ "update", OPTION_MASK_NO_UPDATE, true , true },
{ "vsx", OPTION_MASK_VSX, false, true },
- { "xxsplti32dx", OPTION_MASK_XXSPLTI32DX, false, true },
- { "xxspltiw", OPTION_MASK_XXSPLTIW, false, true },
- { "xxspltidp", OPTION_MASK_XXSPLTIDP, false, true },
#ifdef OPTION_MASK_64BIT
#if TARGET_AIX_OS
{ "aix64", OPTION_MASK_64BIT, false, false },
@@ -28188,7 +27957,7 @@ rs6000_emit_xxspltidp_v2df (rtx dst, long value)
inform (input_location,
"the result for the xxspltidp instruction "
"is undefined for subnormal input values");
- emit_insn (gen_xxspltidp_v2df_internal2 (dst, GEN_INT (value)));
+ emit_insn( gen_xxspltidp_v2df_inst (dst, GEN_INT (value)));
}
/* Implement TARGET_ASM_GENERATE_PIC_ADDR_DIFF_VEC. */
@@ -28211,65 +27980,6 @@ rs6000_output_addr_vec_elt (FILE *file, int value)
fprintf (file, "\n");
}
-/* Sign extend integer values to a given mode. */
-HOST_WIDE_INT
-sign_extend_mode_constant (machine_mode mode, HOST_WIDE_INT value)
-{
- HOST_WIDE_INT mask1;
- HOST_WIDE_INT mask2;
-
- switch (mode)
- {
- default:
- gcc_unreachable ();
-
- case E_QImode:
- mask1 = HOST_WIDE_INT_C (0xff);
- mask2 = HOST_WIDE_INT_C (0x80);
- break;
-
- case E_HImode:
- mask1 = HOST_WIDE_INT_C (0xffff);
- mask2 = HOST_WIDE_INT_C (0x8000);
- break;
-
- case E_SImode:
- mask1 = HOST_WIDE_INT_C (0xffffffff);
- mask2 = HOST_WIDE_INT_C (0x80000000);
- break;
- }
-
- return (((value & mask1) ^ mask2) - mask2);
-}
-
-/* Zero extend integer values to a given mode. */
-unsigned HOST_WIDE_INT
-zero_extend_mode_constant (machine_mode mode, HOST_WIDE_INT value)
-{
- unsigned HOST_WIDE_INT uvalue = (unsigned HOST_WIDE_INT) value;
- unsigned HOST_WIDE_INT mask;
-
- switch (mode)
- {
- default:
- gcc_unreachable ();
-
- case E_QImode:
- mask = HOST_WIDE_INT_UC (0xff);
- break;
-
- case E_HImode:
- mask = HOST_WIDE_INT_UC (0xffff);
- break;
-
- case E_SImode:
- mask = HOST_WIDE_INT_UC (0xffffffff);
- break;
- }
-
- return uvalue & mask;
-}
-
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-rs6000.h"
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 1200c4db6a9..0c76338c734 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -7614,17 +7614,17 @@
;;
;; LWZ LFS LXSSP LXSSPX STFS STXSSP
;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP
-;; MR MT<x> MF<x> NOP XXSPLTIDP XXSPLTI32DX
+;; MR MT<x> MF<x> NOP
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, wY,
Z, m, wa, !r, f, wa,
- !r, *c*l, !r, *h, wa, wa")
+ !r, *c*l, !r, *h")
(match_operand:SF 1 "input_operand"
"m, m, wY, Z, f, v,
wa, r, j, j, f, wa,
- r, r, *h, 0, eF, eD"))]
+ r, r, *h, 0"))]
"(register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))
&& TARGET_HARD_FLOAT
@@ -7646,29 +7646,15 @@
mr %0,%1
mt%0 %1
mf%1 %0
- nop
- #
- #"
+ nop"
[(set_attr "type"
"load, fpload, fpload, fpload, fpstore, fpstore,
fpstore, store, veclogical, integer, fpsimple, fpsimple,
- *, mtjmpr, mfjmpr, *, vecperm, vecperm")
+ *, mtjmpr, mfjmpr, *")
(set_attr "isa"
"*, *, p9v, p8v, *, p9v,
p8v, *, *, *, *, *,
- *, *, *, *, p10, p10")
- (set_attr "prefixed"
- "*, *, *, *, *, *,
- *, *, *, *, *, *,
- *, *, *, *, yes, yes")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *, *,
- *, *, *, *, *, *,
- *, *, *, *, *, 2")
- (set_attr "num_insns"
- "*, *, *, *, *, *,
- *, *, *, *, *, *,
- *, *, *, *, *, 2")])
+ *, *, *, *")])
;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ
;; FMR MR MT%0 MF%1 NOP
@@ -7928,18 +7914,18 @@
;; STFD LFD FMR LXSD STXSD
;; LXSD STXSD XXLOR XXLXOR GPR<-0
-;; LWZ STW MR XXSPLTIDP XXSPLTI32DX
+;; LWZ STW MR
(define_insn "*mov<mode>_hardfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
- Y, r, !r, wa, wa")
+ Y, r, !r")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
- r, Y, r, eF, eD"))]
+ r, Y, r"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -7956,34 +7942,20 @@
#
#
#
- #
- #
#"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, two,
- store, load, two, vecperm, vecperm")
+ store, load, two")
(set_attr "size" "64")
(set_attr "length"
"*, *, *, *, *,
*, *, *, *, 8,
- 8, 8, 8, *, *")
+ 8, 8, 8")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
- *, *, *, p10, p10")
- (set_attr "prefixed"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, yes, yes")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, 2")
- (set_attr "num_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, 2")])
+ *, *, *")])
;; STW LWZ MR G-const H-const F-const
@@ -8010,19 +7982,19 @@
;; STFD LFD FMR LXSD STXSD
;; LXSDX STXSDX XXLOR XXLXOR LI 0
;; STD LD MR MT{CTR,LR} MF{CTR,LR}
-;; NOP MFVSRD MTVSRD XXSPLTIDP XXSPLTI32DX
+;; NOP MFVSRD MTVSRD
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
YZ, r, !r, *c*l, !r,
- *h, r, <f64_dm>, wa, wa")
+ *h, r, <f64_dm>")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
r, YZ, r, r, *h,
- 0, <f64_dm>, r, eF, eD"))]
+ 0, <f64_dm>, r"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8044,35 +8016,18 @@
mf%1 %0
nop
mfvsrd %0,%x1
- mtvsrd %x0,%1
- #
- #"
+ mtvsrd %x0,%1"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, integer,
store, load, *, mtjmpr, mfjmpr,
- *, mfvsr, mtvsr, vecperm, vecperm")
+ *, mfvsr, mtvsr")
(set_attr "size" "64")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
*, *, *, *, *,
- *, p8v, p8v, p10, p10")
- (set_attr "prefixed"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- *, *, *, yes, yes")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, 2")
- (set_attr "num_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, *")])
+ *, p8v, p8v")])
;; STD LD MR MT<SPR> MF<SPR> G-const
;; H-const F-const Special
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 352d4a72ae4..2685fa71517 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -627,15 +627,3 @@ Enable instructions that guard against return-oriented programming attacks.
mprivileged
Target Var(rs6000_privileged) Init(0)
Generate code that will run in privileged state.
-
-mxxspltiw
-Target Undocumented Mask(XXSPLTIW) Var(rs6000_isa_flags)
-Generate (do not generate) XXSPLTIW instructions.
-
-mxxspltidp
-Target Undocumented Mask(XXSPLTIDP) Var(rs6000_isa_flags)
-Generate (do not generate) XXSPLTIDP instructions.
-
-mxxsplti32dx
-Target Undocumented Mask(XXSPLTI32DX) Var(rs6000_isa_flags)
-Generate (do not generate) XXSPLTI32DX instructions.
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 6b7972ca0f6..15a8c0e22d8 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -386,9 +386,9 @@
UNSPEC_VDIVES
UNSPEC_VDIVEU
UNSPEC_XXEVAL
- UNSPEC_XXSPLTIDP
+ UNSPEC_XXSPLTIW
+ UNSPEC_XXSPLTID
UNSPEC_XXSPLTI32DX
- UNSPEC_XXSPLTI32DX_CONST
UNSPEC_XXBLEND
UNSPEC_XXPERMX
])
@@ -6239,10 +6239,41 @@
"vmulld %0,%1,%2"
[(set_attr "type" "veccomplex")])
+;; XXSPLTIW built-in function support
+(define_insn "xxspltiw_v4si"
+ [(set (match_operand:V4SI 0 "register_operand" "=wa")
+ (unspec:V4SI [(match_operand:SI 1 "s32bit_cint_operand" "n")]
+ UNSPEC_XXSPLTIW))]
+ "TARGET_POWER10"
+ "xxspltiw %x0,%1"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
+(define_expand "xxspltiw_v4sf"
+ [(set (match_operand:V4SF 0 "register_operand" "=wa")
+ (unspec:V4SF [(match_operand:SF 1 "const_double_operand" "n")]
+ UNSPEC_XXSPLTIW))]
+ "TARGET_POWER10"
+{
+ long long value = rs6000_const_f32_to_i32 (operands[1]);
+ emit_insn (gen_xxspltiw_v4sf_inst (operands[0], GEN_INT (value)));
+ DONE;
+})
+
+(define_insn "xxspltiw_v4sf_inst"
+ [(set (match_operand:V4SF 0 "register_operand" "=wa")
+ (unspec:V4SF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
+ UNSPEC_XXSPLTIW))]
+ "TARGET_POWER10"
+ "xxspltiw %x0,%1"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
;; XXSPLTIDP built-in function support
(define_expand "xxspltidp_v2df"
- [(use (match_operand:V2DF 0 "register_operand" ))
- (use (match_operand:SF 1 "const_double_operand"))]
+ [(set (match_operand:V2DF 0 "register_operand" )
+ (unspec:V2DF [(match_operand:SF 1 "const_double_operand")]
+ UNSPEC_XXSPLTID))]
"TARGET_POWER10"
{
long value = rs6000_const_f32_to_i32 (operands[1]);
@@ -6250,6 +6281,15 @@
DONE;
})
+(define_insn "xxspltidp_v2df_inst"
+ [(set (match_operand:V2DF 0 "register_operand" "=wa")
+ (unspec:V2DF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
+ UNSPEC_XXSPLTID))]
+ "TARGET_POWER10"
+ "xxspltidp %x0,%1"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
;; XXSPLTI32DX built-in function support
(define_expand "xxsplti32dx_v4si"
[(set (match_operand:V4SI 0 "register_operand" "=wa")
@@ -6380,230 +6420,3 @@
[(set_attr "type" "vecsimple")
(set_attr "prefixed" "yes")])
-;; XXSPLTIW built-in function support. Convert to a vector constant, which
-;; will then be optimized to the XXSPLTIW instruction.
-(define_expand "xxspltiw_v4si"
- [(use (match_operand:V4SI 0 "register_operand"))
- (use (match_operand:SI 1 "s32bit_cint_operand"))]
- "TARGET_POWER10"
-{
- rtx op1 = operands[1];
- rtvec rv = gen_rtvec (4, op1, op1, op1, op1);
- rtx vec_constant = gen_rtx_CONST_VECTOR (V4SImode, rv);
- emit_move_insn (operands[0], vec_constant);
-})
-
-(define_expand "xxspltiw_v4sf"
- [(use (match_operand:V4SF 0 "register_operand"))
- (use (match_operand:SF 1 "const_double_operand"))]
- "TARGET_POWER10"
-{
- rtx op1 = operands[1];
- rtvec rv = gen_rtvec (4, op1, op1, op1, op1);
- rtx vec_constant = gen_rtx_CONST_VECTOR (V4SFmode, rv);
- emit_move_insn (operands[0], vec_constant);
-})
-
-;; XXSPLTIW support. Add support for the XXSPLTIW built-in functions, and to
-;; use XXSPLTIW to load up vector V8HImode, V4SImode, and V4SFmode vector
-;; constants where all elements are the the same. We special case loading up
-;; integer -16..15 and floating point 0.0f, since we can use the shorter
-;; XXSPLTIB, VSPLTISH, and VSPLTISW instructions.
-
-(define_insn "*xxspltiw_v8hi_dup"
- [(set (match_operand:V8HI 0 "vsx_register_operand" "=wa,wa,v,wa")
- (vec_duplicate:V8HI
- (match_operand 1 "const_int_operand" "O,wM,wB,n")))]
- "TARGET_XXSPLTIW"
-{
- HOST_WIDE_INT value = INTVAL (operands[1]);
- unsigned HOST_WIDE_INT uns_value = zero_extend_mode_constant (HImode, value);
- HOST_WIDE_INT sign_value = sign_extend_mode_constant (HImode, uns_value);
-
- if (sign_value == 0)
- return "xxspltib %x0,0";
-
- if (sign_value == -1)
- return "xxspltib %x0,255";
-
- int r = reg_or_subregno (operands[0]);
- if (ALTIVEC_REGNO_P (r) && EASY_VECTOR_15 (sign_value))
- {
- operands[2] = GEN_INT (sign_value);
- return "vspltish %0,%1";
- }
-
- /* The assembler doesn't like negative values. */
- HOST_WIDE_INT new_value = (uns_value << 16) | uns_value;
- operands[2] = GEN_INT (zero_extend_mode_constant (SImode, new_value));
- return "xxspltiw %x0,%2";
-}
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "*,*,*,yes")])
-
-(define_insn "*xxspltiw_v4si_dup"
- [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,wa,v,wa")
- (vec_duplicate:V4SI
- (match_operand 1 "const_int_operand" "O,wM,wB,n")))]
- "TARGET_XXSPLTIW"
-{
- HOST_WIDE_INT value = INTVAL (operands[1]);
- unsigned HOST_WIDE_INT uns_value = zero_extend_mode_constant (SImode, value);
- HOST_WIDE_INT sign_value = sign_extend_mode_constant (SImode, uns_value);
-
- if (sign_value == 0)
- return "xxspltib %x0,0";
-
- if (sign_value == -1)
- return "xxspltib %x0,255";
-
- int r = reg_or_subregno (operands[0]);
- if (ALTIVEC_REGNO_P (r) && EASY_VECTOR_15 (sign_value))
- {
- operands[2] = GEN_INT (sign_value);
- return "vspltisw %0,%2";
- }
-
- /* The assembler doesn't like negative values. */
- operands[2] = GEN_INT (uns_value);
- return "xxspltiw %x0,%2";
-}
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "*,*,*,yes")])
-
-(define_insn "xxspltiw_v4sf_dup"
- [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa")
- (vec_duplicate:V4SF
- (match_operand:SF 1 "const_double_operand" "O,F")))]
- "TARGET_XXSPLTIW"
-{
- if (operands[1] == CONST0_RTX (SFmode))
- return "xxspltib %x0,0";
-
- /* The assembler doesn't like negative values. */
- long value = rs6000_const_f32_to_i32 (operands[1]);
- operands[2] = GEN_INT (zero_extend_mode_constant (SImode, value));
- return "xxspltiw %x0,%2";
-}
- [(set_attr "type" "vecsimple")
- (set_attr "prefixed" "*,yes")])
-
-;; Convert vector constant to vec_duplicate.
-(define_mode_iterator XXSPLTIW [V8HI V4SI V4SF])
-
-(define_split
- [(set (match_operand:XXSPLTIW 0 "vsx_register_operand")
- (match_operand:XXSPLTIW 1 "xxspltiw_operand"))]
- "TARGET_XXSPLTIW && GET_CODE (operands[1]) == CONST_VECTOR"
- [(set (match_dup 0)
- (vec_duplicate:<MODE> (match_dup 2)))]
-{
- operands[2] = CONST_VECTOR_ELT (operands[1], 0);
-})
-
-;; Generate the XXSPLTIDP instruction to support SFmode and DFmode scalar
-;; constants and V2DF vector constants where both elements are the same. The
-;; constant has be expressible as a SFmode constant that is not a SFmode
-;; denormal value.
-(define_mode_iterator XXSPLTIDP [SF DF V2DF])
-
-(define_insn_and_split "*xxspltidp_<mode>_internal1"
- [(set (match_operand:XXSPLTIDP 0 "vsx_register_operand" "=wa")
- (match_operand:XXSPLTIDP 1 "xxspltidp_operand"))]
- "TARGET_XXSPLTIDP"
- "#"
- "&& 1"
- [(set (match_operand:XXSPLTIDP 0 "vsx_register_operand")
- (unspec:XXSPLTIDP [(match_dup 2)] UNSPEC_XXSPLTIDP))]
-{
- HOST_WIDE_INT value = 0;
-
- if (!xxspltidp_constant_p (operands[1], <MODE>mode, &value))
- gcc_unreachable ();
-
- operands[2] = GEN_INT (value);
-}
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-;; Just in case the user issued -mno-xxspltidp, allow the built-in function
-;; even if the compiler does not automatically generate XXSPLTIDP.
-(define_insn "xxspltidp_<mode>_internal2"
- [(set (match_operand:XXSPLTIDP 0 "vsx_register_operand" "=wa")
- (unspec:XXSPLTIDP [(match_operand 1 "const_int_operand" "n")]
- UNSPEC_XXSPLTIDP))]
- "TARGET_POWER10"
- "xxspltidp %x0,%1"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-;; XXSPLTI32DX used to create 64-bit constants or vector constants where the
-;; even elements match and the odd elements match.
-(define_mode_iterator XXSPLTI32DX [SF DF V2DF V2DI])
-
-(define_insn_and_split "*xxsplti32dx_<mode>"
- [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa")
- (match_operand:XXSPLTI32DX 1 "xxsplti32dx_operand"))]
- "TARGET_XXSPLTI32DX"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (unspec:XXSPLTI32DX [(match_dup 2)
- (match_dup 3)] UNSPEC_XXSPLTI32DX_CONST))
- (set (match_dup 0)
- (unspec:XXSPLTI32DX [(match_dup 0)
- (match_dup 4)
- (match_dup 5)] UNSPEC_XXSPLTI32DX_CONST))]
-{
- HOST_WIDE_INT high = 0, low = 0;
-
- if (!xxsplti32dx_constant_p (operands[1], <MODE>mode, &high, &low))
- gcc_unreachable ();
-
- /* If the low bits are 0 or all 1s, initialize that word first. This way we
- can use a smaller XXSPLTIB instruction instead the first XXSPLTI32DX. */
- if (low == 0 || low == -1)
- {
- operands[2] = const1_rtx;
- operands[3] = GEN_INT (low);
- operands[4] = const0_rtx;
- operands[5] = GEN_INT (high);
- }
- else
- {
- operands[2] = const0_rtx;
- operands[3] = GEN_INT (high);
- operands[4] = const1_rtx;
- operands[5] = GEN_INT (low);
- }
-}
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")
- (set_attr "num_insns" "2")
- (set_attr "max_prefixed_insns" "2")])
-
-;; First word of XXSPLTI32DX
-(define_insn "*xxsplti32dx_<mode>_first"
- [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa,wa,wa")
- (unspec:XXSPLTI32DX [(match_operand 1 "u1bit_cint_operand" "n,n,n")
- (match_operand 2 "const_int_operand" "O,wM,n")]
- UNSPEC_XXSPLTI32DX_CONST))]
- "TARGET_XXSPLTI32DX"
- "@
- xxspltib %x0,0
- xxspltib %x0,255
- xxsplti32dx %x0,%1,%2"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "*,*,yes")])
-
-;; Second word of XXSPLTI32DX
-(define_insn "*xxsplti32dx_<mode>_second"
- [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa")
- (unspec:XXSPLTI32DX [(match_operand:XXSPLTI32DX 1 "vsx_register_operand" "0")
- (match_operand 2 "u1bit_cint_operand" "n")
- (match_operand 3 "const_int_operand" "n")]
- UNSPEC_XXSPLTI32DX_CONST))]
- "TARGET_XXSPLTI32DX"
- "xxsplti32dx %x0,%2,%3"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
diff --git a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv.c b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv.c
index 8a00aaca70d..f312550f04d 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv.c
@@ -8,13 +8,6 @@
/* { dg-require-effective-target lp64 } */
/* { dg-options "-maltivec -O3 -fwrapv " } */
-/* If the compiler is generating power10 instructions, turn it off. Otherwise,
- it will generate a XXSPLTIW instruction instead of LXV/LXVD2X. */
-
-#ifdef _ARCH_PWR10
-#pragma GCC target ("cpu=power9")
-#endif
-
#include <altivec.h>
/* original test as reported. */
vector unsigned int splat(void)
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
deleted file mode 100644
index 1435ef4ef4f..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-double
-scalar_double_0 (void)
-{
- return 0.0; /* XXSPLTIB or XXLXOR. */
-}
-
-double
-scalar_double_1 (void)
-{
- return 1.0; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-double
-scalar_double_m0 (void)
-{
- return -0.0; /* XXSPLTIDP. */
-}
-
-double
-scalar_double_nan (void)
-{
- return __builtin_nan (""); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_inf (void)
-{
- return __builtin_inf (); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inf ();
-}
-#endif
-
-double
-scalar_double_pi (void)
-{
- return M_PI; /* 2x XXSPLTI32DX. */
-}
-
-double
-scalar_double_denorm (void)
-{
- return 0x1p-149f; /* XXSPLTIB, XXSPLTI32DX. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
-/* { dg-final { scan-assembler-not {\mplfd\M} } } */
-/* { dg-final { scan-assembler-not {\mplxsd\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
deleted file mode 100644
index e9a45d5159d..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating SFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-float
-scalar_float_0 (void)
-{
- return 0.0f; /* XXSPLTIB or XXLXOR. */
-}
-
-float
-scalar_float_1 (void)
-{
- return 1.0f; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-float
-scalar_float_m0 (void)
-{
- return -0.0f; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_nan (void)
-{
- return __builtin_nanf (""); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_inf (void)
-{
- return __builtin_inff (); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inff ();
-}
-#endif
-
-float
-scalar_float_pi (void)
-{
- return (float)M_PI; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_denorm (void)
-{
- return 0x1p-149f; /* PLFS. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mplfs\M} } } */
-/* { dg-final { scan-assembler-not {\mplxssp\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
deleted file mode 100644
index d81198b163d..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating V2DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-vector double
-v2df_double_0 (void)
-{
- return (vector double) { 0.0, 0.0 }; /* XXSPLTIB or XXLXOR. */
-}
-
-vector double
-v2df_double_1 (void)
-{
- return (vector double) { 1.0, 1.0 }; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-vector double
-v2df_double_m0 (void)
-{
- return (vector double) { -0.0, -0.0 }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_nan (void)
-{
- return (vector double) { __builtin_nan (""),
- __builtin_nan ("") }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_inf (void)
-{
- return (vector double) { __builtin_inf (),
- __builtin_inf () }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_m_inf (void)
-{
- return (vector double) { - __builtin_inf (),
- - __builtin_inf () }; /* XXSPLTIDP. */
-}
-#endif
-
-vector double
-v2df_double_pi (void)
-{
- return (vector double) { M_PI, M_PI }; /* 2x XXSPLTI32DX. */
-}
-
-vector double
-v2df_double_denorm (void)
-{
- return (vector double) { (double)0x1p-149f, /* XXSPLTIB, */
- (double)0x1p-149f }; /* XXSPLTI32DX. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
deleted file mode 100644
index 06830b02076..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SF vector constants. */
-
-vector float
-v4sf_const_1 (void)
-{
- return (vector float) { 1.0f, 1.0f, 1.0f, 1.0f }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_nan (void)
-{
- return (vector float) { __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf ("") }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_inf (void)
-{
- return (vector float) { __builtin_inff (),
- __builtin_inff (),
- __builtin_inff (),
- __builtin_inff () }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_m0 (void)
-{
- return (vector float) { -0.0f, -0.0f, -0.0f, -0.0f }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_1 (void)
-{
- return vec_splats (1.0f); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_nan (void)
-{
- return vec_splats (__builtin_nanf ("")); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_inf (void)
-{
- return vec_splats (__builtin_inff ()); /* XXSPLTIW. */
-}
-
-vector float
-v8hi_splats_m0 (void)
-{
- return vec_splats (-0.0f); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 8 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
deleted file mode 100644
index 02d0c6d66a2..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SI vector constants. We make sure
- the power9 support (XXSPLTIB/VEXTSB2W) is not done. */
-
-vector int
-v4si_const_1 (void)
-{
- return (vector int) { 1, 1, 1, 1 }; /* VSLTPISW. */
-}
-
-vector int
-v4si_const_126 (void)
-{
- return (vector int) { 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_const_1023 (void)
-{
- return (vector int) { 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_splats_1 (void)
-{
- return vec_splats (1); /* VSLTPISW. */
-}
-
-vector int
-v4si_splats_126 (void)
-{
- return vec_splats (126); /* XXSPLTIW. */
-}
-
-vector int
-v8hi_splats_1023 (void)
-{
- return vec_splats (1023); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mvspltisw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvextsb2w\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
deleted file mode 100644
index e6d0fab6d67..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V8HI vector constants. We make sure
- the power9 support (XXSPLTIB/VUPKLSB) is not done. */
-
-vector short
-v8hi_const_1 (void)
-{
- return (vector short) { 1, 1, 1, 1, 1, 1, 1, 1 }; /* VSLTPISH. */
-}
-
-vector short
-v8hi_const_126 (void)
-{
- return (vector short) { 126, 126, 126, 126,
- 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_const_1023 (void)
-{
- return (vector short) { 1023, 1023, 1023, 1023,
- 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1 (void)
-{
- return vec_splats ((short)1); /* VSLTPISH. */
-}
-
-vector short
-v8hi_splats_126 (void)
-{
- return vec_splats ((short)126); /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1023 (void)
-{
- return vec_splats ((short)1023); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mvspltish\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvupklsb\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
index f49ef91422e..a135279b1d7 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
@@ -149,6 +149,8 @@ main (int argc, char *argv [])
return 0;
}
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxxspltiw\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
+
+
next reply other threads:[~2021-05-20 12:31 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-20 12:31 Michael Meissner [this message]
-- strict thread matches above, loose matches on Subject: below --
2021-05-25 5:14 Michael Meissner
2021-05-19 14:19 Michael Meissner
2021-05-18 16:07 Michael Meissner
2021-05-18 1:28 Michael Meissner
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210520123154.6B3D63848032@sourceware.org \
--to=meissner@gcc.gnu.org \
--cc=gcc-cvs@gcc.gnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).