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From: Christophe Lyon <clyon@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/clyon/heads/mve-autovec)] arm: Auto-vectorization for MVE: vaddv Date: Fri, 21 May 2021 16:14:32 +0000 (GMT) [thread overview] Message-ID: <20210521161432.85DCB3851C3A@sourceware.org> (raw) https://gcc.gnu.org/g:f5acca021becbf6e39ffd5249c2fd554ea030ca5 commit f5acca021becbf6e39ffd5249c2fd554ea030ca5 Author: Christophe Lyon <christophe.lyon@linaro.org> Date: Fri May 21 16:12:58 2021 +0000 arm: Auto-vectorization for MVE: vaddv Diff: --- gcc/config/arm/mve.md | 2 +- gcc/config/arm/neon.md | 13 ------------- gcc/config/arm/vec-common.md | 26 +++++++++++++++++++++++++ gcc/testsuite/gcc.target/arm/simd/mve-vaddv-1.c | 26 +++++++++++++++++++++++++ 4 files changed, 53 insertions(+), 14 deletions(-) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 133ebe93cf3..0a6ba80c99d 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -464,7 +464,7 @@ ;; ;; [vaddvq_s, vaddvq_u]) ;; -(define_insn "mve_vaddvq_<supf><mode>" +(define_insn "@mve_vaddvq_<supf><mode>" [ (set (match_operand:SI 0 "s_register_operand" "=Te") (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")] diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 977adef5490..6a6573317cf 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -1161,19 +1161,6 @@ DONE; }) -(define_expand "reduc_plus_scal_<mode>" - [(match_operand:<V_elem> 0 "nonimmediate_operand") - (match_operand:VQ 1 "s_register_operand")] - "ARM_HAVE_NEON_<MODE>_ARITH && !BYTES_BIG_ENDIAN" -{ - rtx step1 = gen_reg_rtx (<V_HALF>mode); - - emit_insn (gen_quad_halves_plus<mode> (step1, operands[1])); - emit_insn (gen_reduc_plus_scal_<V_half> (operands[0], step1)); - - DONE; -}) - (define_expand "reduc_plus_scal_v2di" [(match_operand:DI 0 "nonimmediate_operand") (match_operand:V2DI 1 "s_register_operand")] diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index e8b2901b006..cc136e2865f 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -539,3 +539,29 @@ emit_insn (gen_mve_vst4q<mode> (operands[0], operands[1])); DONE; }) + +(define_expand "reduc_plus_scal_<mode>" + [(match_operand:<V_elem> 0 "nonimmediate_operand") + (match_operand:VQ 1 "s_register_operand")] + "ARM_HAVE_NEON_<MODE>_ARITH || (TARGET_HAVE_MVE && <MODE>mode != V4SFmode) + && !TARGET_REALLY_IWMMXT + && !BYTES_BIG_ENDIAN" +{ + if (TARGET_NEON) + { + rtx step1 = gen_reg_rtx (<V_HALF>mode); + + emit_insn (gen_quad_halves_plus<mode> (step1, operands[1])); + emit_insn (gen_reduc_plus_scal_<V_half> (operands[0], step1)); + } + else + { + /* vaddv generates a 32 bits accumulator. */ + rtx op0 = gen_reg_rtx (SImode); + + emit_insn (gen_mve_vaddvq (VADDVQ_S, <MODE>mode, op0, operands[1])); + emit_insn (gen_rtx_SET (operands[0], gen_rtx_SUBREG (<V_elem>mode, op0, 0))); + } + + DONE; +}) diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vaddv-1.c b/gcc/testsuite/gcc.target/arm/simd/mve-vaddv-1.c new file mode 100644 index 00000000000..b6b0bc368f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vaddv-1.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O3" } */ + +#include <stdint.h> + +#define FUNC(SIGN, TYPE, BITS, NB) \ + TYPE##32_t test_ ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t *a) { \ + int i; \ + TYPE##BITS##_t result = 0; \ + for (i=0; i<NB; i++) { \ + result += a[i]; \ + } \ + return result; \ +} + +/* 128-bit vectors. */ +FUNC(s, int, 8, 16) +FUNC(u, uint, 8, 16) +FUNC(s, int, 16, 8) +FUNC(u, uint, 16, 8) +FUNC(s, int, 32, 4) +FUNC(u, uint, 32, 4) + +/* { dg-final { scan-assembler-times {vaddv\.s} 6 } } */
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