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* [gcc r12-1020] Fusion patterns for add-logical/logical-add
@ 2021-05-24 19:47 Aaron Sawdey
0 siblings, 0 replies; only message in thread
From: Aaron Sawdey @ 2021-05-24 19:47 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:a8764071f2eb6b4cdc9ecb788dfaa2b095b52598
commit r12-1020-ga8764071f2eb6b4cdc9ecb788dfaa2b095b52598
Author: Aaron Sawdey <acsawdey@linux.ibm.com>
Date: Tue Mar 2 18:06:37 2021 -0600
Fusion patterns for add-logical/logical-add
This patch modifies the function in genfusion.pl for generating
the logical-logical patterns so that it can also generate the
add-logical and logical-add patterns which are very similar.
gcc/ChangeLog:
* config/rs6000/genfusion.pl (gen_logical_addsubf): Refactor to
add generation of logical-add and add-logical fusion pairs.
* config/rs6000/rs6000-cpus.def: Add new fusion to ISA 3.1 mask
and powerpc mask.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Turn on
logical-add and add-logical fusion by default.
* config/rs6000/rs6000.opt: Add -mpower10-fusion-logical-add and
-mpower10-fusion-add-logical options.
* config/rs6000/fusion.md: Regenerate file.
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/fusion-p10-logadd.c: New file.
Diff:
---
gcc/config/rs6000/fusion.md | 872 +++++++++++++++------
gcc/config/rs6000/genfusion.pl | 83 +-
gcc/config/rs6000/rs6000-cpus.def | 4 +
gcc/config/rs6000/rs6000.c | 8 +
gcc/config/rs6000/rs6000.opt | 12 +-
.../gcc.target/powerpc/fusion-p10-logadd.c | 97 +++
6 files changed, 797 insertions(+), 279 deletions(-)
diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md
index 4d810e6ba13..51912106663 100644
--- a/gcc/config/rs6000/fusion.md
+++ b/gcc/config/rs6000/fusion.md
@@ -355,11 +355,11 @@
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar and -> and
(define_insn "*fuse_and_and"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (and:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (and:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
(match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r"))
(match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -373,11 +373,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar andc -> and
(define_insn "*fuse_andc_and"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -391,11 +391,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar eqv -> and
(define_insn "*fuse_eqv_and"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
(match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -409,11 +409,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar nand -> and
(define_insn "*fuse_nand_and"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
(match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -427,11 +427,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar nor -> and
(define_insn "*fuse_nor_and"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
(match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -445,11 +445,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar or -> and
(define_insn "*fuse_or_and"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (and:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (and:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -463,11 +463,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar orc -> and
(define_insn "*fuse_orc_and"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -481,11 +481,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar xor -> and
(define_insn "*fuse_xor_and"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (and:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (and:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -499,11 +499,47 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; add-logical fusion pattern generated by gen_logical_addsubf
+;; scalar add -> and
+(define_insn "*fuse_add_and"
+ [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
+ (and:GPR (plus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
+ (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
+ (clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
+ "(TARGET_P10_FUSION && TARGET_P10_FUSION_ADDLOG)"
+ "@
+ add %3,%1,%0\;and %3,%3,%2
+ add %3,%1,%0\;and %3,%3,%2
+ add %3,%1,%0\;and %3,%3,%2
+ add %4,%1,%0\;and %3,%4,%2"
+ [(set_attr "type" "fused_arith_logical")
+ (set_attr "cost" "6")
+ (set_attr "length" "8")])
+
+;; add-logical fusion pattern generated by gen_logical_addsubf
+;; scalar subf -> and
+(define_insn "*fuse_subf_and"
+ [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
+ (and:GPR (minus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
+ (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
+ (clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
+ "(TARGET_P10_FUSION && TARGET_P10_FUSION_ADDLOG)"
+ "@
+ subf %3,%1,%0\;and %3,%3,%2
+ subf %3,%1,%0\;and %3,%3,%2
+ subf %3,%1,%0\;and %3,%3,%2
+ subf %4,%1,%0\;and %3,%4,%2"
+ [(set_attr "type" "fused_arith_logical")
+ (set_attr "cost" "6")
+ (set_attr "length" "8")])
+
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar and -> andc
(define_insn "*fuse_and_andc"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (and:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (and:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -517,11 +553,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar andc -> andc
(define_insn "*fuse_andc_andc"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -535,11 +571,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar eqv -> andc
(define_insn "*fuse_eqv_andc"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -553,11 +589,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar nand -> andc
(define_insn "*fuse_nand_andc"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -571,11 +607,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar nor -> andc
(define_insn "*fuse_nor_andc"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -589,11 +625,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar or -> andc
(define_insn "*fuse_or_andc"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (and:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (and:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -607,11 +643,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar orc -> andc
(define_insn "*fuse_orc_andc"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -625,11 +661,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar xor -> andc
(define_insn "*fuse_xor_andc"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (and:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (and:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -643,11 +679,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar and -> eqv
(define_insn "*fuse_and_eqv"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (not:GPR (xor:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (not:GPR (xor:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -661,11 +697,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar andc -> eqv
(define_insn "*fuse_andc_eqv"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (not:GPR (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (not:GPR (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -679,11 +715,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar eqv -> eqv
(define_insn "*fuse_eqv_eqv"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (not:GPR (xor:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (not:GPR (xor:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
(match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")))
(match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -697,11 +733,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar nand -> eqv
(define_insn "*fuse_nand_eqv"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (not:GPR (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (not:GPR (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
(match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -715,11 +751,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar nor -> eqv
(define_insn "*fuse_nor_eqv"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (not:GPR (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (not:GPR (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
(match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -733,11 +769,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar or -> eqv
(define_insn "*fuse_or_eqv"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (not:GPR (xor:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (not:GPR (xor:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -751,11 +787,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar orc -> eqv
(define_insn "*fuse_orc_eqv"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (not:GPR (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (not:GPR (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -769,11 +805,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar xor -> eqv
(define_insn "*fuse_xor_eqv"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (not:GPR (xor:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (not:GPR (xor:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -787,11 +823,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar and -> nand
(define_insn "*fuse_and_nand"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (ior:GPR (not:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (ior:GPR (not:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -805,11 +841,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar andc -> nand
(define_insn "*fuse_andc_nand"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (ior:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (ior:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -823,11 +859,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar eqv -> nand
(define_insn "*fuse_eqv_nand"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (ior:GPR (not:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (ior:GPR (not:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))))
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -841,11 +877,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar nand -> nand
(define_insn "*fuse_nand_nand"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (ior:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (ior:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))))
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -859,11 +895,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar nor -> nand
(define_insn "*fuse_nor_nand"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (ior:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (ior:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))))
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -877,11 +913,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar or -> nand
(define_insn "*fuse_or_nand"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (ior:GPR (not:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (ior:GPR (not:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -895,11 +931,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar orc -> nand
(define_insn "*fuse_orc_nand"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (ior:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (ior:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -913,11 +949,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar xor -> nand
(define_insn "*fuse_xor_nand"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -931,11 +967,47 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; add-logical fusion pattern generated by gen_logical_addsubf
+;; scalar add -> nand
+(define_insn "*fuse_add_nand"
+ [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
+ (ior:GPR (not:GPR (plus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
+ (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
+ (clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
+ "(TARGET_P10_FUSION && TARGET_P10_FUSION_ADDLOG)"
+ "@
+ add %3,%1,%0\;nand %3,%3,%2
+ add %3,%1,%0\;nand %3,%3,%2
+ add %3,%1,%0\;nand %3,%3,%2
+ add %4,%1,%0\;nand %3,%4,%2"
+ [(set_attr "type" "fused_arith_logical")
+ (set_attr "cost" "6")
+ (set_attr "length" "8")])
+
+;; add-logical fusion pattern generated by gen_logical_addsubf
+;; scalar subf -> nand
+(define_insn "*fuse_subf_nand"
+ [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
+ (ior:GPR (not:GPR (minus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
+ (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
+ (clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
+ "(TARGET_P10_FUSION && TARGET_P10_FUSION_ADDLOG)"
+ "@
+ subf %3,%1,%0\;nand %3,%3,%2
+ subf %3,%1,%0\;nand %3,%3,%2
+ subf %3,%1,%0\;nand %3,%3,%2
+ subf %4,%1,%0\;nand %3,%4,%2"
+ [(set_attr "type" "fused_arith_logical")
+ (set_attr "cost" "6")
+ (set_attr "length" "8")])
+
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar and -> nor
(define_insn "*fuse_and_nor"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (and:GPR (not:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (and:GPR (not:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -949,11 +1021,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar andc -> nor
(define_insn "*fuse_andc_nor"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (and:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (and:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -967,11 +1039,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar eqv -> nor
(define_insn "*fuse_eqv_nor"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (and:GPR (not:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (and:GPR (not:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))))
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -985,11 +1057,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar nand -> nor
(define_insn "*fuse_nand_nor"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (and:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (and:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))))
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -1003,11 +1075,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar nor -> nor
(define_insn "*fuse_nor_nor"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (and:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (and:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))))
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -1021,11 +1093,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar or -> nor
(define_insn "*fuse_or_nor"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (and:GPR (not:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (and:GPR (not:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -1039,11 +1111,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar orc -> nor
(define_insn "*fuse_orc_nor"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (and:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (and:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -1057,11 +1129,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar xor -> nor
(define_insn "*fuse_xor_nor"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -1075,11 +1147,47 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; add-logical fusion pattern generated by gen_logical_addsubf
+;; scalar add -> nor
+(define_insn "*fuse_add_nor"
+ [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
+ (and:GPR (not:GPR (plus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
+ (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
+ (clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
+ "(TARGET_P10_FUSION && TARGET_P10_FUSION_ADDLOG)"
+ "@
+ add %3,%1,%0\;nor %3,%3,%2
+ add %3,%1,%0\;nor %3,%3,%2
+ add %3,%1,%0\;nor %3,%3,%2
+ add %4,%1,%0\;nor %3,%4,%2"
+ [(set_attr "type" "fused_arith_logical")
+ (set_attr "cost" "6")
+ (set_attr "length" "8")])
+
+;; add-logical fusion pattern generated by gen_logical_addsubf
+;; scalar subf -> nor
+(define_insn "*fuse_subf_nor"
+ [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
+ (and:GPR (not:GPR (minus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
+ (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
+ (clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
+ "(TARGET_P10_FUSION && TARGET_P10_FUSION_ADDLOG)"
+ "@
+ subf %3,%1,%0\;nor %3,%3,%2
+ subf %3,%1,%0\;nor %3,%3,%2
+ subf %3,%1,%0\;nor %3,%3,%2
+ subf %4,%1,%0\;nor %3,%4,%2"
+ [(set_attr "type" "fused_arith_logical")
+ (set_attr "cost" "6")
+ (set_attr "length" "8")])
+
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar and -> or
(define_insn "*fuse_and_or"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (ior:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (ior:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -1093,11 +1201,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar andc -> or
(define_insn "*fuse_andc_or"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -1111,11 +1219,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar eqv -> or
(define_insn "*fuse_eqv_or"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
(match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -1129,11 +1237,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar nand -> or
(define_insn "*fuse_nand_or"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
(match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -1147,11 +1255,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar nor -> or
(define_insn "*fuse_nor_or"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
(match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -1165,11 +1273,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar or -> or
(define_insn "*fuse_or_or"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (ior:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (ior:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
(match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r"))
(match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -1183,11 +1291,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar orc -> or
(define_insn "*fuse_orc_or"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -1201,11 +1309,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar xor -> or
(define_insn "*fuse_xor_or"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (ior:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (ior:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -1219,11 +1327,47 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; add-logical fusion pattern generated by gen_logical_addsubf
+;; scalar add -> or
+(define_insn "*fuse_add_or"
+ [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
+ (ior:GPR (plus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
+ (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
+ (clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
+ "(TARGET_P10_FUSION && TARGET_P10_FUSION_ADDLOG)"
+ "@
+ add %3,%1,%0\;or %3,%3,%2
+ add %3,%1,%0\;or %3,%3,%2
+ add %3,%1,%0\;or %3,%3,%2
+ add %4,%1,%0\;or %3,%4,%2"
+ [(set_attr "type" "fused_arith_logical")
+ (set_attr "cost" "6")
+ (set_attr "length" "8")])
+
+;; add-logical fusion pattern generated by gen_logical_addsubf
+;; scalar subf -> or
+(define_insn "*fuse_subf_or"
+ [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
+ (ior:GPR (minus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
+ (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
+ (clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
+ "(TARGET_P10_FUSION && TARGET_P10_FUSION_ADDLOG)"
+ "@
+ subf %3,%1,%0\;or %3,%3,%2
+ subf %3,%1,%0\;or %3,%3,%2
+ subf %3,%1,%0\;or %3,%3,%2
+ subf %4,%1,%0\;or %3,%4,%2"
+ [(set_attr "type" "fused_arith_logical")
+ (set_attr "cost" "6")
+ (set_attr "length" "8")])
+
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar and -> orc
(define_insn "*fuse_and_orc"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (ior:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (ior:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -1237,11 +1381,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar andc -> orc
(define_insn "*fuse_andc_orc"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -1255,11 +1399,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar eqv -> orc
(define_insn "*fuse_eqv_orc"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -1273,11 +1417,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar nand -> orc
(define_insn "*fuse_nand_orc"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -1291,11 +1435,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar nor -> orc
(define_insn "*fuse_nor_orc"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -1309,11 +1453,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar or -> orc
(define_insn "*fuse_or_orc"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (ior:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (ior:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -1327,11 +1471,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar orc -> orc
(define_insn "*fuse_orc_orc"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -1345,11 +1489,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar xor -> orc
(define_insn "*fuse_xor_orc"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (ior:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (ior:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -1363,11 +1507,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar and -> xor
(define_insn "*fuse_and_xor"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (xor:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (xor:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -1381,11 +1525,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar andc -> xor
(define_insn "*fuse_andc_xor"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -1399,11 +1543,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar eqv -> xor
(define_insn "*fuse_eqv_xor"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (xor:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (xor:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
(match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -1417,11 +1561,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar nand -> xor
(define_insn "*fuse_nand_xor"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
(match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -1435,11 +1579,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar nor -> xor
(define_insn "*fuse_nor_xor"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
(match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -1453,11 +1597,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar or -> xor
(define_insn "*fuse_or_xor"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (xor:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (xor:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -1471,11 +1615,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar orc -> xor
(define_insn "*fuse_orc_xor"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
(match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -1489,11 +1633,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; scalar xor -> xor
(define_insn "*fuse_xor_xor"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
- (xor:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (xor:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
(match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r"))
(match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
@@ -1507,11 +1651,227 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-add fusion pattern generated by gen_logical_addsubf
+;; scalar and -> add
+(define_insn "*fuse_and_add"
+ [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
+ (plus:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
+ (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
+ (clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
+ "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)"
+ "@
+ and %3,%1,%0\;add %3,%3,%2
+ and %3,%1,%0\;add %3,%3,%2
+ and %3,%1,%0\;add %3,%3,%2
+ and %4,%1,%0\;add %3,%4,%2"
+ [(set_attr "type" "fused_arith_logical")
+ (set_attr "cost" "6")
+ (set_attr "length" "8")])
+
+;; logical-add fusion pattern generated by gen_logical_addsubf
+;; scalar nand -> add
+(define_insn "*fuse_nand_add"
+ [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
+ (plus:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
+ (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
+ (clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
+ "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)"
+ "@
+ nand %3,%1,%0\;add %3,%3,%2
+ nand %3,%1,%0\;add %3,%3,%2
+ nand %3,%1,%0\;add %3,%3,%2
+ nand %4,%1,%0\;add %3,%4,%2"
+ [(set_attr "type" "fused_arith_logical")
+ (set_attr "cost" "6")
+ (set_attr "length" "8")])
+
+;; logical-add fusion pattern generated by gen_logical_addsubf
+;; scalar nor -> add
+(define_insn "*fuse_nor_add"
+ [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
+ (plus:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
+ (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
+ (clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
+ "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)"
+ "@
+ nor %3,%1,%0\;add %3,%3,%2
+ nor %3,%1,%0\;add %3,%3,%2
+ nor %3,%1,%0\;add %3,%3,%2
+ nor %4,%1,%0\;add %3,%4,%2"
+ [(set_attr "type" "fused_arith_logical")
+ (set_attr "cost" "6")
+ (set_attr "length" "8")])
+
+;; logical-add fusion pattern generated by gen_logical_addsubf
+;; scalar or -> add
+(define_insn "*fuse_or_add"
+ [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
+ (plus:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
+ (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
+ (clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
+ "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)"
+ "@
+ or %3,%1,%0\;add %3,%3,%2
+ or %3,%1,%0\;add %3,%3,%2
+ or %3,%1,%0\;add %3,%3,%2
+ or %4,%1,%0\;add %3,%4,%2"
+ [(set_attr "type" "fused_arith_logical")
+ (set_attr "cost" "6")
+ (set_attr "length" "8")])
+
+;; logical-add fusion pattern generated by gen_logical_addsubf
+;; scalar and -> subf
+(define_insn "*fuse_and_subf"
+ [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
+ (minus:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
+ (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
+ (clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
+ "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)"
+ "@
+ and %3,%1,%0\;subf %3,%3,%2
+ and %3,%1,%0\;subf %3,%3,%2
+ and %3,%1,%0\;subf %3,%3,%2
+ and %4,%1,%0\;subf %3,%4,%2"
+ [(set_attr "type" "fused_arith_logical")
+ (set_attr "cost" "6")
+ (set_attr "length" "8")])
+
+;; logical-add fusion pattern generated by gen_logical_addsubf
+;; scalar nand -> subf
+(define_insn "*fuse_nand_subf"
+ [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
+ (minus:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
+ (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
+ (clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
+ "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)"
+ "@
+ nand %3,%1,%0\;subf %3,%3,%2
+ nand %3,%1,%0\;subf %3,%3,%2
+ nand %3,%1,%0\;subf %3,%3,%2
+ nand %4,%1,%0\;subf %3,%4,%2"
+ [(set_attr "type" "fused_arith_logical")
+ (set_attr "cost" "6")
+ (set_attr "length" "8")])
+
+;; logical-add fusion pattern generated by gen_logical_addsubf
+;; scalar nor -> subf
+(define_insn "*fuse_nor_subf"
+ [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
+ (minus:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))
+ (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
+ (clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
+ "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)"
+ "@
+ nor %3,%1,%0\;subf %3,%3,%2
+ nor %3,%1,%0\;subf %3,%3,%2
+ nor %3,%1,%0\;subf %3,%3,%2
+ nor %4,%1,%0\;subf %3,%4,%2"
+ [(set_attr "type" "fused_arith_logical")
+ (set_attr "cost" "6")
+ (set_attr "length" "8")])
+
+;; logical-add fusion pattern generated by gen_logical_addsubf
+;; scalar or -> subf
+(define_insn "*fuse_or_subf"
+ [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
+ (minus:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))
+ (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
+ (clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
+ "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)"
+ "@
+ or %3,%1,%0\;subf %3,%3,%2
+ or %3,%1,%0\;subf %3,%3,%2
+ or %3,%1,%0\;subf %3,%3,%2
+ or %4,%1,%0\;subf %3,%4,%2"
+ [(set_attr "type" "fused_arith_logical")
+ (set_attr "cost" "6")
+ (set_attr "length" "8")])
+
+;; logical-add fusion pattern generated by gen_logical_addsubf
+;; scalar and -> rsubf
+(define_insn "*fuse_and_rsubf"
+ [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
+ (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")
+ (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))))
+ (clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
+ "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)"
+ "@
+ and %3,%1,%0\;subf %3,%2,%3
+ and %3,%1,%0\;subf %3,%2,%3
+ and %3,%1,%0\;subf %3,%2,%3
+ and %4,%1,%0\;subf %3,%2,%4"
+ [(set_attr "type" "fused_arith_logical")
+ (set_attr "cost" "6")
+ (set_attr "length" "8")])
+
+;; logical-add fusion pattern generated by gen_logical_addsubf
+;; scalar nand -> rsubf
+(define_insn "*fuse_nand_rsubf"
+ [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
+ (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")
+ (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))))
+ (clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
+ "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)"
+ "@
+ nand %3,%1,%0\;subf %3,%2,%3
+ nand %3,%1,%0\;subf %3,%2,%3
+ nand %3,%1,%0\;subf %3,%2,%3
+ nand %4,%1,%0\;subf %3,%2,%4"
+ [(set_attr "type" "fused_arith_logical")
+ (set_attr "cost" "6")
+ (set_attr "length" "8")])
+
+;; logical-add fusion pattern generated by gen_logical_addsubf
+;; scalar nor -> rsubf
+(define_insn "*fuse_nor_rsubf"
+ [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
+ (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")
+ (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r"))
+ (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))))
+ (clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
+ "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)"
+ "@
+ nor %3,%1,%0\;subf %3,%2,%3
+ nor %3,%1,%0\;subf %3,%2,%3
+ nor %3,%1,%0\;subf %3,%2,%3
+ nor %4,%1,%0\;subf %3,%2,%4"
+ [(set_attr "type" "fused_arith_logical")
+ (set_attr "cost" "6")
+ (set_attr "length" "8")])
+
+;; logical-add fusion pattern generated by gen_logical_addsubf
+;; scalar or -> rsubf
+(define_insn "*fuse_or_rsubf"
+ [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r")
+ (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")
+ (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")
+ (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))))
+ (clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
+ "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)"
+ "@
+ or %3,%1,%0\;subf %3,%2,%3
+ or %3,%1,%0\;subf %3,%2,%3
+ or %3,%1,%0\;subf %3,%2,%3
+ or %4,%1,%0\;subf %3,%2,%4"
+ [(set_attr "type" "fused_arith_logical")
+ (set_attr "cost" "6")
+ (set_attr "length" "8")])
+
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vand -> vand
(define_insn "*fuse_vand_vand"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
+ (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
(match_operand:VM 1 "altivec_register_operand" "%v,v,v,v"))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -1525,11 +1885,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vandc -> vand
(define_insn "*fuse_vandc_vand"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
+ (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -1543,11 +1903,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector veqv -> vand
(define_insn "*fuse_veqv_vand"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
+ (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -1561,11 +1921,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnand -> vand
(define_insn "*fuse_vnand_vand"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
+ (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
(not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -1579,11 +1939,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnor -> vand
(define_insn "*fuse_vnor_vand"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
+ (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
(not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -1597,11 +1957,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vor -> vand
(define_insn "*fuse_vor_vand"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
+ (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -1615,11 +1975,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vorc -> vand
(define_insn "*fuse_vorc_vand"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
+ (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -1633,11 +1993,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vxor -> vand
(define_insn "*fuse_vxor_vand"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
+ (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -1651,11 +2011,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vand -> vandc
(define_insn "*fuse_vand_vandc"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
+ (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
(not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -1669,11 +2029,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vandc -> vandc
(define_insn "*fuse_vandc_vandc"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
+ (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
(not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -1687,11 +2047,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector veqv -> vandc
(define_insn "*fuse_veqv_vandc"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
+ (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))
(not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -1705,11 +2065,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnand -> vandc
(define_insn "*fuse_vnand_vandc"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
+ (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
(not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))
(not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -1723,11 +2083,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnor -> vandc
(define_insn "*fuse_vnor_vandc"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
+ (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
(not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))
(not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -1741,11 +2101,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vor -> vandc
(define_insn "*fuse_vor_vandc"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
+ (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
(not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -1759,11 +2119,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vorc -> vandc
(define_insn "*fuse_vorc_vandc"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
+ (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
(not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -1777,11 +2137,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vxor -> vandc
(define_insn "*fuse_vxor_vandc"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
+ (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
(not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -1795,11 +2155,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vand -> veqv
(define_insn "*fuse_vand_veqv"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (not:VM (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
+ (not:VM (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -1813,11 +2173,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vandc -> veqv
(define_insn "*fuse_vandc_veqv"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
+ (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -1831,11 +2191,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector veqv -> veqv
(define_insn "*fuse_veqv_veqv"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (not:VM (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
+ (not:VM (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
(match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -1849,11 +2209,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnand -> veqv
(define_insn "*fuse_vnand_veqv"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
+ (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
(not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -1867,11 +2227,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnor -> veqv
(define_insn "*fuse_vnor_veqv"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
+ (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
(not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -1885,11 +2245,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vor -> veqv
(define_insn "*fuse_vor_veqv"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (not:VM (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
+ (not:VM (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -1903,11 +2263,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vorc -> veqv
(define_insn "*fuse_vorc_veqv"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
+ (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -1921,11 +2281,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vxor -> veqv
(define_insn "*fuse_vxor_veqv"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (not:VM (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
+ (not:VM (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -1939,11 +2299,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vand -> vnand
(define_insn "*fuse_vand_vnand"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (ior:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
+ (ior:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))
(not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -1957,11 +2317,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vandc -> vnand
(define_insn "*fuse_vandc_vnand"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
+ (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))
(not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -1975,11 +2335,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector veqv -> vnand
(define_insn "*fuse_veqv_vnand"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (ior:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
+ (ior:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))))
(not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -1993,11 +2353,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnand -> vnand
(define_insn "*fuse_vnand_vnand"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
+ (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
(not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))))
(not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2011,11 +2371,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnor -> vnand
(define_insn "*fuse_vnor_vnand"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
+ (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
(not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))))
(not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2029,11 +2389,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vor -> vnand
(define_insn "*fuse_vor_vnand"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (ior:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
+ (ior:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))
(not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2047,11 +2407,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vorc -> vnand
(define_insn "*fuse_vorc_vnand"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
+ (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))
(not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2065,11 +2425,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vxor -> vnand
(define_insn "*fuse_vxor_vnand"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
+ (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))
(not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2083,11 +2443,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vand -> vnor
(define_insn "*fuse_vand_vnor"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (and:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
+ (and:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))
(not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2101,11 +2461,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vandc -> vnor
(define_insn "*fuse_vandc_vnor"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
+ (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))
(not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2119,11 +2479,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector veqv -> vnor
(define_insn "*fuse_veqv_vnor"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (and:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
+ (and:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))))
(not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2137,11 +2497,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnand -> vnor
(define_insn "*fuse_vnand_vnor"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
+ (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
(not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))))
(not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2155,11 +2515,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnor -> vnor
(define_insn "*fuse_vnor_vnor"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
+ (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
(not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))))
(not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2173,11 +2533,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vor -> vnor
(define_insn "*fuse_vor_vnor"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (and:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
+ (and:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))
(not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2191,11 +2551,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vorc -> vnor
(define_insn "*fuse_vorc_vnor"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
+ (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))
(not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2209,11 +2569,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vxor -> vnor
(define_insn "*fuse_vxor_vnor"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
+ (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))
(not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2227,11 +2587,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vand -> vor
(define_insn "*fuse_vand_vor"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
+ (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2245,11 +2605,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vandc -> vor
(define_insn "*fuse_vandc_vor"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
+ (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2263,11 +2623,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector veqv -> vor
(define_insn "*fuse_veqv_vor"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
+ (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2281,11 +2641,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnand -> vor
(define_insn "*fuse_vnand_vor"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
+ (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
(not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2299,11 +2659,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnor -> vor
(define_insn "*fuse_vnor_vor"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
+ (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
(not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2317,11 +2677,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vor -> vor
(define_insn "*fuse_vor_vor"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
+ (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
(match_operand:VM 1 "altivec_register_operand" "%v,v,v,v"))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2335,11 +2695,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vorc -> vor
(define_insn "*fuse_vorc_vor"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
+ (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2353,11 +2713,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vxor -> vor
(define_insn "*fuse_vxor_vor"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
+ (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2371,11 +2731,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vand -> vorc
(define_insn "*fuse_vand_vorc"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
+ (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
(not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2389,11 +2749,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vandc -> vorc
(define_insn "*fuse_vandc_vorc"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
+ (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
(not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2407,11 +2767,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector veqv -> vorc
(define_insn "*fuse_veqv_vorc"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
+ (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))
(not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2425,11 +2785,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnand -> vorc
(define_insn "*fuse_vnand_vorc"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
+ (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
(not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))
(not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2443,11 +2803,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnor -> vorc
(define_insn "*fuse_vnor_vorc"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
+ (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
(not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))
(not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2461,11 +2821,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vor -> vorc
(define_insn "*fuse_vor_vorc"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
+ (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
(not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2479,11 +2839,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vorc -> vorc
(define_insn "*fuse_vorc_vorc"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
+ (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
(not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2497,11 +2857,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vxor -> vorc
(define_insn "*fuse_vxor_vorc"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
+ (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
(not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2515,11 +2875,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vand -> vxor
(define_insn "*fuse_vand_vxor"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
+ (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2533,11 +2893,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vandc -> vxor
(define_insn "*fuse_vandc_vxor"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
+ (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2551,11 +2911,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector veqv -> vxor
(define_insn "*fuse_veqv_vxor"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
+ (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2569,11 +2929,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnand -> vxor
(define_insn "*fuse_vnand_vxor"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
+ (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
(not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2587,11 +2947,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnor -> vxor
(define_insn "*fuse_vnor_vxor"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
+ (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
(not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2605,11 +2965,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vor -> vxor
(define_insn "*fuse_vor_vxor"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
+ (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2623,11 +2983,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vorc -> vxor
(define_insn "*fuse_vorc_vxor"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
+ (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
@@ -2641,11 +3001,11 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
-;; logical-logical fusion pattern generated by gen_2logical
+;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vxor -> vxor
(define_insn "*fuse_vxor_vxor"
[(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v")
- (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
+ (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
(match_operand:VM 1 "altivec_register_operand" "%v,v,v,v"))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
(clobber (match_scratch:VM 4 "=X,X,X,&r"))]
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index 1fd46cc0604..1285dd42043 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -144,23 +144,32 @@ sub gen_ld_cmpi_p10
}
}
-sub gen_2logical
+sub gen_logical_addsubf
{
my @logicals = ( "and", "andc", "eqv", "nand", "nor", "or", "orc", "xor" );
+ my %logicals_addsub = ( "and"=>1, "nand"=>1, "nor"=>1, "or"=>1 );
+ my @addsub = ( "add", "subf" );
+ my %isaddsub = ( "add"=>1, "subf"=>1 );
my %complement = ( "and"=> 0, "andc"=> 1, "eqv"=> 0, "nand"=> 3,
- "nor"=> 3, "or"=> 0, "orc"=> 1, "xor"=> 0 );
+ "nor"=> 3, "or"=> 0, "orc"=> 1, "xor"=> 0,
+ "add"=> 0, "subf"=> 0 );
my %invert = ( "and"=> 0, "andc"=> 0, "eqv"=> 1, "nand"=> 0,
- "nor"=> 0, "or"=> 0, "orc"=> 0, "xor"=> 0 );
+ "nor"=> 0, "or"=> 0, "orc"=> 0, "xor"=> 0,
+ "add"=> 0, "subf"=> 0 );
my %commute2 = ( "and"=> 1, "andc"=> 0, "eqv"=> 1, "nand"=> 0,
"nor"=> 0, "or"=> 1, "orc"=> 0, "xor"=> 1 );
my %rtlop = ( "and"=>"and", "andc"=>"and", "eqv"=>"xor", "nand"=>"ior",
- "nor"=>"and", "or"=>"ior", "orc"=>"ior", "xor"=>"xor" );
+ "nor"=>"and", "or"=>"ior", "orc"=>"ior", "xor"=>"xor",
+ "add"=>"plus", "subf"=>"minus" );
- my ($kind, $vchr, $mode, $pred, $constraint, $cr, $outer, $outer_op,
- $outer_comp, $outer_inv, $outer_rtl, $inner, $inner_comp, $inner_inv,
- $inner_rtl, $inner_op, $both_commute, $c4, $bc, $inner_arg0,
- $inner_arg1, $inner_exp, $outer_arg2, $outer_exp, $insn, $fuse_type);
+ my ($kind, $vchr, $mode, $pred, $constraint, $cr, $outer, @outer_ops,
+ $outer_op, $outer_comp, $outer_inv, $outer_rtl, $inner, @inner_ops,
+ $inner_comp, $inner_inv, $inner_rtl, $inner_op, $both_commute, $c4,
+ $bc, $inner_arg0, $inner_arg1, $inner_exp, $outer_arg2, $outer_exp,
+ $target_flag, $ftype, $insn, $is_rsubf, $outer_32, $outer_42,
+ $outer_name, $fuse_type);
KIND: foreach $kind ('scalar','vector') {
+ @outer_ops = @logicals;
if ( $kind eq 'vector' ) {
$vchr = "v";
$mode = "VM";
@@ -173,14 +182,37 @@ sub gen_2logical
$pred = "gpc_reg_operand";
$constraint = "r";
$fuse_type = "fused_arith_logical";
+ push (@outer_ops, @addsub);
+ push (@outer_ops, ( "rsubf" ));
}
$c4 = "${constraint},${constraint},${constraint},${constraint}";
- OUTER: foreach $outer ( @logicals ) {
+ OUTER: foreach $outer ( @outer_ops ) {
+ $outer_name = "${vchr}${outer}";
+ if ( $outer eq "rsubf" ) {
+ $is_rsubf = 1;
+ $outer = "subf";
+ } else {
+ $is_rsubf = 0;
+ }
$outer_op = "${vchr}${outer}";
$outer_comp = $complement{$outer};
$outer_inv = $invert{$outer};
$outer_rtl = $rtlop{$outer};
- INNER: foreach $inner ( @logicals ) {
+ @inner_ops = @logicals;
+ $ftype = "logical-logical";
+ $target_flag = "TARGET_P10_FUSION_2LOGICAL";
+ if ( exists $isaddsub{$outer} ) {
+ @inner_ops = sort keys %logicals_addsub;
+ $ftype = "logical-add";
+ $target_flag = "TARGET_P10_FUSION_LOGADD";
+ } elsif ( $kind ne 'vector' && exists $logicals_addsub{$outer} ) {
+ push (@inner_ops, @addsub);
+ }
+ INNER: foreach $inner ( @inner_ops ) {
+ if ( exists $isaddsub{$inner} ) {
+ $ftype = "add-logical";
+ $target_flag = "TARGET_P10_FUSION_ADDLOG";
+ }
$inner_comp = $complement{$inner};
$inner_inv = $invert{$inner};
$inner_rtl = $rtlop{$inner};
@@ -197,7 +229,7 @@ sub gen_2logical
if ( ($inner_comp & 2) == 2 ) {
$inner_arg1 = "(not:${mode} $inner_arg1)";
}
- $inner_exp = "(${inner_rtl}:${mode} ${inner_arg0}
+ $inner_exp = "(${inner_rtl}:${mode} ${inner_arg0}
${inner_arg1})";
if ( $inner_inv == 1 ) {
$inner_exp = "(not:${mode} $inner_exp)";
@@ -209,26 +241,35 @@ sub gen_2logical
if ( ($outer_comp & 2) == 2 ) {
$inner_exp = "(not:${mode} $inner_exp)";
}
- $outer_exp = "(${outer_rtl}:${mode} ${inner_exp}
+ if ( $is_rsubf == 1 ) {
+ $outer_exp = "(${outer_rtl}:${mode} ${outer_arg2}
+ ${inner_exp})";
+ $outer_32 = "%2,%3";
+ $outer_42 = "%2,%4";
+ } else {
+ $outer_exp = "(${outer_rtl}:${mode} ${inner_exp}
${outer_arg2})";
+ $outer_32 = "%3,%2";
+ $outer_42 = "%4,%2";
+ }
if ( $outer_inv == 1 ) {
$outer_exp = "(not:${mode} $outer_exp)";
}
$insn = <<"EOF";
-;; logical-logical fusion pattern generated by gen_2logical
-;; $kind $inner_op -> $outer_op
-(define_insn "*fuse_${inner_op}_${outer_op}"
+;; $ftype fusion pattern generated by gen_logical_addsubf
+;; $kind $inner_op -> $outer_name
+(define_insn "*fuse_${inner_op}_${outer_name}"
[(set (match_operand:${mode} 3 "${pred}" "=0,1,&${constraint},${constraint}")
${outer_exp})
(clobber (match_scratch:${mode} 4 "=X,X,X,&r"))]
- "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
+ "(TARGET_P10_FUSION && $target_flag)"
"@
- ${inner_op} %3,%1,%0\\;${outer_op} %3,%3,%2
- ${inner_op} %3,%1,%0\\;${outer_op} %3,%3,%2
- ${inner_op} %3,%1,%0\\;${outer_op} %3,%3,%2
- ${inner_op} %4,%1,%0\\;${outer_op} %3,%4,%2"
+ ${inner_op} %3,%1,%0\\;${outer_op} %3,${outer_32}
+ ${inner_op} %3,%1,%0\\;${outer_op} %3,${outer_32}
+ ${inner_op} %3,%1,%0\\;${outer_op} %3,${outer_32}
+ ${inner_op} %4,%1,%0\\;${outer_op} %3,${outer_42}"
[(set_attr "type" "$fuse_type")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -284,7 +325,7 @@ EOF
}
gen_ld_cmpi_p10();
-gen_2logical();
+gen_logical_addsubf();
gen_addadd;
exit(0);
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index d46a91dd11b..52ce84835f7 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -86,6 +86,8 @@
| OPTION_MASK_P10_FUSION \
| OPTION_MASK_P10_FUSION_LD_CMPI \
| OPTION_MASK_P10_FUSION_2LOGICAL \
+ | OPTION_MASK_P10_FUSION_LOGADD \
+ | OPTION_MASK_P10_FUSION_ADDLOG \
| OPTION_MASK_P10_FUSION_2ADD)
/* Flags that need to be turned off if -mno-power9-vector. */
@@ -136,6 +138,8 @@
| OPTION_MASK_P10_FUSION \
| OPTION_MASK_P10_FUSION_LD_CMPI \
| OPTION_MASK_P10_FUSION_2LOGICAL \
+ | OPTION_MASK_P10_FUSION_LOGADD \
+ | OPTION_MASK_P10_FUSION_ADDLOG \
| OPTION_MASK_P10_FUSION_2ADD \
| OPTION_MASK_HTM \
| OPTION_MASK_ISEL \
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 9f03256065e..835af7708f9 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -4477,6 +4477,14 @@ rs6000_option_override_internal (bool global_init_p)
&& (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_2LOGICAL) == 0)
rs6000_isa_flags |= OPTION_MASK_P10_FUSION_2LOGICAL;
+ if (TARGET_POWER10
+ && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_LOGADD) == 0)
+ rs6000_isa_flags |= OPTION_MASK_P10_FUSION_LOGADD;
+
+ if (TARGET_POWER10
+ && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_ADDLOG) == 0)
+ rs6000_isa_flags |= OPTION_MASK_P10_FUSION_ADDLOG;
+
if (TARGET_POWER10
&& (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_2ADD) == 0)
rs6000_isa_flags |= OPTION_MASK_P10_FUSION_2ADD;
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index e30dc040651..0538db387dc 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -500,11 +500,19 @@ Fuse certain integer operations together for better performance on power10.
mpower10-fusion-2logical
Target Undocumented Mask(P10_FUSION_2LOGICAL) Var(rs6000_isa_flags)
-Fuse certain integer operations together for better performance on power10.
+Fuse pairs of scalar or vector logical operations together for better performance on power10.
+
+mpower10-fusion-logical-add
+Target Undocumented Mask(P10_FUSION_LOGADD) Var(rs6000_isa_flags)
+Fuse scalar logical op with add/subf for better performance on power10.
+
+mpower10-fusion-add-logical
+Target Undocumented Mask(P10_FUSION_ADDLOG) Var(rs6000_isa_flags)
+Fuse scalar add/subf with logical op for better performance on power10.
mpower10-fusion-2add
Target Undocumented Mask(P10_FUSION_2ADD) Var(rs6000_isa_flags)
-Fuse certain add operations together for better performance on power10.
+Fuse dependent pairs of add or vaddudm instructions for better performance on power10.
mcrypto
Target Mask(CRYPTO) Var(rs6000_isa_flags)
diff --git a/gcc/testsuite/gcc.target/powerpc/fusion-p10-logadd.c b/gcc/testsuite/gcc.target/powerpc/fusion-p10-logadd.c
new file mode 100644
index 00000000000..b7022b2b61d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fusion-p10-logadd.c
@@ -0,0 +1,97 @@
+/* { dg-do compile } */
+/* { dg-options "-mdejagnu-cpu=power10 -O3 -dp" } */
+
+#include <altivec.h>
+#include <stdint.h>
+
+#define ADD(a,b) ((a)+(b))
+#define SUB1(a,b) ((a)-(b))
+#define SUB2(a,b) ((b)-(a))
+
+/* and/andc/eqv/nand/nor/or/orc/xor */
+#define AND(a,b) ((a)&(b))
+#define NAND(a,b) (~((a)&(b)))
+#define NOR(a,b) (~((a)|(b)))
+#define OR(a,b) ((a)|(b))
+#define TEST1(type, func) \
+ type func ## _add_T_ ## type (type a, type b, type c) { return ADD(func(a,b),c); } \
+ type func ## _sub1_T_ ## type (type a, type b, type c) { return SUB1(func(a,b),c); } \
+ type func ## _sub2_T_ ## type (type a, type b, type c) { return SUB2(func(a,b),c); } \
+ type func ## _rev_add_T_ ## type (type a, type b, type c) { return ADD(c,func(a,b)); } \
+ type func ## _rev_sub1_T_ ## type (type a, type b, type c) { return SUB1(c,func(a,b)); } \
+ type func ## _rev_sub2_T_ ## type (type a, type b, type c) { return SUB2(c,func(a,b)); }
+#define TEST2(type, func) \
+ type func ## _and_T_ ## type (type a, type b, type c) { return AND(func(a,b),c); } \
+ type func ## _nand_T_ ## type (type a, type b, type c) { return NAND(func(a,b),c); } \
+ type func ## _or_T_ ## type (type a, type b, type c) { return OR(func(a,b),c); } \
+ type func ## _nor_T_ ## type (type a, type b, type c) { return NOR(func(a,b),c); } \
+ type func ## _rev_and_T_ ## type (type a, type b, type c) { return AND(c,func(a,b)); } \
+ type func ## _rev_nand_T_ ## type (type a, type b, type c) { return NAND(c,func(a,b)); } \
+ type func ## _rev_or_T_ ## type (type a, type b, type c) { return OR(c,func(a,b)); } \
+ type func ## _rev_nor_T_ ## type (type a, type b, type c) { return NOR(c,func(a,b)); }
+#define TEST(type) \
+ TEST1(type,AND) \
+ TEST1(type,NAND) \
+ TEST1(type,NOR) \
+ TEST1(type,OR) \
+ TEST2(type,ADD) \
+ TEST2(type,SUB1) \
+ TEST2(type,SUB2)
+
+typedef vector bool char vboolchar_t;
+typedef vector unsigned int vuint_t;
+
+TEST(uint8_t);
+TEST(int8_t);
+TEST(uint16_t);
+TEST(int16_t);
+TEST(uint32_t);
+TEST(int32_t);
+TEST(uint64_t);
+TEST(int64_t);
+
+/* { dg-final { scan-assembler-times "fuse_nand_rsubf/0" 2 } } */
+/* { dg-final { scan-assembler-times "fuse_nand_rsubf/2" 2 } } */
+/* { dg-final { scan-assembler-times "fuse_nor_rsubf/0" 2 } } */
+/* { dg-final { scan-assembler-times "fuse_nor_rsubf/2" 2 } } */
+/* { dg-final { scan-assembler-times "fuse_add_nand/0" 4 } } */
+/* { dg-final { scan-assembler-times "fuse_add_nor/0" 4 } } */
+/* { dg-final { scan-assembler-times "fuse_add_or/0" 4 } } */
+/* { dg-final { scan-assembler-times "fuse_and_rsubf/0" 4 } } */
+/* { dg-final { scan-assembler-times "fuse_and_subf/0" 4 } } */
+/* { dg-final { scan-assembler-times "fuse_nand_add/0" 4 } } */
+/* { dg-final { scan-assembler-times "fuse_nand_subf/0" 4 } } */
+/* { dg-final { scan-assembler-times "fuse_nor_add/0" 4 } } */
+/* { dg-final { scan-assembler-times "fuse_nor_subf/0" 4 } } */
+/* { dg-final { scan-assembler-times "fuse_or_rsubf/0" 4 } } */
+/* { dg-final { scan-assembler-times "fuse_or_subf/0" 4 } } */
+/* { dg-final { scan-assembler-times "fuse_subf_nand/0" 4 } } */
+/* { dg-final { scan-assembler-times "fuse_subf_nand/1" 4 } } */
+/* { dg-final { scan-assembler-times "fuse_subf_nor/0" 4 } } */
+/* { dg-final { scan-assembler-times "fuse_subf_nor/1" 4 } } */
+/* { dg-final { scan-assembler-times "fuse_subf_or/0" 4 } } */
+/* { dg-final { scan-assembler-times "fuse_subf_or/1" 4 } } */
+/* { dg-final { scan-assembler-times "fuse_and_add/0" 6 } } */
+/* { dg-final { scan-assembler-times "fuse_or_add/0" 6 } } */
+/* { dg-final { scan-assembler-times "fuse_add_and/0" 8 } } */
+/* { dg-final { scan-assembler-times "fuse_add_and/2" 8 } } */
+/* { dg-final { scan-assembler-times "fuse_subf_and/0" 8 } } */
+/* { dg-final { scan-assembler-times "fuse_subf_and/1" 8 } } */
+/* { dg-final { scan-assembler-times "fuse_add_nand/2" 12 } } */
+/* { dg-final { scan-assembler-times "fuse_add_nor/2" 12 } } */
+/* { dg-final { scan-assembler-times "fuse_add_or/2" 12 } } */
+/* { dg-final { scan-assembler-times "fuse_and_rsubf/2" 12 } } */
+/* { dg-final { scan-assembler-times "fuse_and_subf/2" 12 } } */
+/* { dg-final { scan-assembler-times "fuse_nand_add/2" 12 } } */
+/* { dg-final { scan-assembler-times "fuse_nand_subf/2" 12 } } */
+/* { dg-final { scan-assembler-times "fuse_nor_add/2" 12 } } */
+/* { dg-final { scan-assembler-times "fuse_nor_subf/2" 12 } } */
+/* { dg-final { scan-assembler-times "fuse_or_rsubf/2" 12 } } */
+/* { dg-final { scan-assembler-times "fuse_or_subf/2" 12 } } */
+/* { dg-final { scan-assembler-times "fuse_subf_and/2" 16 } } */
+/* { dg-final { scan-assembler-times "fuse_and_add/2" 22 } } */
+/* { dg-final { scan-assembler-times "fuse_or_add/2" 22 } } */
+/* { dg-final { scan-assembler-times "fuse_subf_nand/2" 24 } } */
+/* { dg-final { scan-assembler-times "fuse_subf_nor/2" 24 } } */
+/* { dg-final { scan-assembler-times "fuse_subf_or/2" 24 } } */
+
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2021-05-24 19:47 [gcc r12-1020] Fusion patterns for add-logical/logical-add Aaron Sawdey
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