[gcc(refs/users/meissner/heads/work053)] Update ChangeLog.meissner.

[gcc(refs/users/meissner/heads/work053)] Update ChangeLog.meissner.

[Michael Meissner]

https://gcc.gnu.org/g:da6c0e7e8886a393052ad31f604d167a0547aaa0

commit da6c0e7e8886a393052ad31f604d167a0547aaa0
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Tue Jun 1 17:47:36 2021 -0400

    Update ChangeLog.meissner.
    
    gcc/
    2021-06-01  Michael Meissner  <meissner@linux.ibm.com>
    
            * ChangeLog.meissner: Update.
    
    gcc/testsuite/
    2021-06-01  Michael Meissner  <meissner@linux.ibm.com>
    
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner           | 8 ++++++++
 gcc/testsuite/ChangeLog.meissner | 5 +++++
 2 files changed, 13 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 835332b2704..671380f5d16 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,11 @@
+work053.patch016:
+2021-06-01  Michael Meissner  <meissner@linux.ibm.com>
+
+	* config/rs6000/rs6000.md (udivti3): New insn.
+	(divti3): New insn.
+	(umodti3): New insn.
+	(modti3): New insn.
+
 work053.patch015:
 2021-05-25  Michael Meissner  <meissner@linux.ibm.com>
 
diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner
index 18574fd365d..3bebcf9aeff 100644
--- a/gcc/testsuite/ChangeLog.meissner
+++ b/gcc/testsuite/ChangeLog.meissner
@@ -1,3 +1,8 @@
+work053.patch016:
+2021-06-01  Michael Meissner  <meissner@linux.ibm.com>
+
+	* gcc.target/powerpc/p10-vdiv-vmod.c: New test.
+
 work053.patch015:
 2021-05-25  Michael Meissner  <meissner@linux.ibm.com>

[gcc(refs/users/meissner/heads/work053)] Update ChangeLog.meissner.

[Michael Meissner]

https://gcc.gnu.org/g:b1597df31416b4bf431796faaf12a1d89d688ec2

commit b1597df31416b4bf431796faaf12a1d89d688ec2
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Jun 2 13:20:10 2021 -0400

    Update ChangeLog.meissner.
    
    gcc/
    2021-06-02  Michael Meissner  <meissner@linux.ibm.com>
    
            * ChangeLog.meissner: Update.
    
    gcc/testsuite/
    2021-06-02  Michael Meissner  <meissner@linux.ibm.com>
    
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner           | 63 ++++++++++++++++++++++++++++++++++++++++
 gcc/testsuite/ChangeLog.meissner | 12 ++++++++
 2 files changed, 75 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 671380f5d16..71c426de148 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,66 @@
+work053.patch017:
+2021-06-02  Michael Meissner  <meissner@linux.ibm.com>
+
+	PR target/93230
+	* config/rs6000/rs6000.c (rs6000_split_vec_extract_var): Remove
+	support for handling MEM, users call rs6000_adjust_vec_address
+	directly.
+	* config/rs6000/vsx.md (VSX_EX_FL): New mode attribute.
+	(vsx_extract_v4sf_<mode>_load): Rename to vsx_extract_v4sf_load.
+	(vsx_extract_v4sf_to_df_load): New insn to combine vec_extract of
+	SFmode from memory being converted to DFmode.
+	(vsx_extract_v4si_<su><mode>_load): New insn to support V4SI
+	vec_extract from memory being converted to DImode directly without
+	an extra sign/zero extension.
+	(vsx_extract_v8hi_<su><mode>_load): New insn to support V8HI
+	vec_extract from memory being converted to DImode directly without
+	an extra sign/zero extension.
+	(vsx_extract_v16qi_u<mode>_load): New insn to support V16QI
+	vec_extract from memory being converted to DImode directly without
+	an extra zero extension.
+	(vsx_extract_v4si_var_load): Split V4SI extract from other small
+	integers, and add support for loading up vector registers with
+	sign/zero extension directly.
+	(vsx_extract_<mode>_var_load, VSX_EXTRACT_I2 iterator): Split
+	V8HI/V16QI vector extract from memory to handle loading vector
+	registers in addition to GPR registers.
+	(vsx_extract_<mode>_uns_di_var): New insn to optimize extracting a
+	small integer from a vector in a register and zero extending it to
+	DImode.
+	(vsx_extract_v4si_<su><mode>_var_load): New insns to support
+	combining a V4SI variable vector extract from memory with sign or
+	zero extension.
+	(vsx_extract_v8hi_<su><mode>_var_load): New insns to support
+	combining a V8HI variable vector extract from memory with sign or
+	zero extension.
+	(vsx_extract_v4si_u<mode>_var_load): New insns to support
+	combining a V16QI variable vector extract from memory with zero
+	extension.
+	(vsx_ext_v4si_fl_<mode>_load): New insn to support a V4SI vector
+	extract that is converted to floating point to avoid doing a
+	direct move.
+	(vsx_ext_v4si_ufl_<mode>_load):  New insn to support an unsigned
+	V4SI vector extract that is converted to floating point to avoid
+	doing a direct move.
+	(vsx_ext_v4si_fl_<mode>_var_load): New insn to support a V4SI
+	variable vector extract that is converted to floating point to
+	avoid doing a direct move.
+	(vsx_ext_v4si_ufl_<mode>_var_load): New insn to support an
+	unsigned V4SI variable vector extract that is converted to
+	floating point to avoid doing a direct move.
+	(vsx_ext_<VSX_EXTRACT_I2:mode>_fl_<FL_CONV:mode>_load): New insns
+	to support a V8HI/V16QI vector extract that is converted to
+	floating point to avoid doing a direct move.
+	(vsx_ext_<VSX_EXTRACT_I2:mode>_ufl_<FL_CONV:mode>_load): New insns
+	to support an unsigned V8HI/V16QI vector extract that is converted
+	to floating point to avoid doing a direct move.
+	(vsx_ext_<VSX_EXTRACT_I2:mode>_fl_<FL_CONV:mode>_vl): New insns to
+	support a variable V8HI/V16QI vector extract that is converted to
+	floating point to avoid doing a direct move.
+	(vsx_ext_<VSX_EXTRACT_I2:mode>_ufl_<FL_CONV:mode>_vl): New insns
+	to support an unsigned variable V8HI/V16QI vector extract that is
+	converted to floating point to avoid doing a direct move.
+
 work053.patch016:
 2021-06-01  Michael Meissner  <meissner@linux.ibm.com>
 
diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner
index 3bebcf9aeff..797d030a266 100644
--- a/gcc/testsuite/ChangeLog.meissner
+++ b/gcc/testsuite/ChangeLog.meissner
@@ -1,3 +1,15 @@
+work053.patch017:
+2021-06-02  Michael Meissner  <meissner@linux.ibm.com>
+
+	PR target/93230
+	* gcc.target/powerpc/fold-vec-extract-char.p8.c: Adjust
+	instruction counts.
+	* gcc.target/powerpc/fold-vec-extract-int.p8.c: Adjust
+	instruction counts.
+	* gcc.target/powerpc/fold-vec-extract-short.p8.c: Adjust
+	instruction counts.
+	* gcc.target/powerpc/pcrel-opt-inc-di.c: Fix typo.
+
 work053.patch016:
 2021-06-01  Michael Meissner  <meissner@linux.ibm.com>

[gcc(refs/users/meissner/heads/work053)] Update ChangeLog.meissner.

[Michael Meissner]

https://gcc.gnu.org/g:cb03e2eb31db2c600eeb18c4a38e5d1c773f0230

commit cb03e2eb31db2c600eeb18c4a38e5d1c773f0230
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Tue May 25 01:21:54 2021 -0400

    Update ChangeLog.meissner.
    
    gcc/
    2021-05-25  Michael Meissner  <meissner@linux.ibm.com>
    
            * ChangeLog.meissner: Update.
    
    gcc/testsuite/
    2021-05-25  Michael Meissner  <meissner@linux.ibm.com>
    
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner           | 5 ++++-
 gcc/testsuite/ChangeLog.meissner | 4 ++--
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index becf9c4f039..835332b2704 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -20,7 +20,7 @@ work053.patch015:
 	(vsx_mov<mode>_32bit): Add support to generate lxvkq.
 
 work053.patch014:
-2021-05-20  Michael Meissner  <meissner@linux.ibm.com>
+2021-05-25  Michael Meissner  <meissner@linux.ibm.com>
 
 	* config/rs6000/constraint.md (eD): New constraint.
 	* config/rs6000/predicates.md (easy_fp_constant): If the constant
@@ -30,6 +30,9 @@ work053.patch014:
 	XXSPLTI32DX, it is easy.
 	* config/rs6000/rs6000-protos.h (xxsplti32dx_constant_p): New
 	declaration.
+	* config/rs6000/rs6000-cpus.h (ISA_3_1_MASKS_SERVER): Add
+	-mxxsplti32dx.
+	(POWERPC_MASKS): Add -mxxsplti32dx.
 	* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
 	support for -mxxsplti32dx.
 	(xxsplti32dx_constant_float_p): New helper function.
diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner
index 2ec74805406..18574fd365d 100644
--- a/gcc/testsuite/ChangeLog.meissner
+++ b/gcc/testsuite/ChangeLog.meissner
@@ -1,10 +1,10 @@
 work053.patch015:
-2021-05-20  Michael Meissner  <meissner@linux.ibm.com>
+2021-05-25  Michael Meissner  <meissner@linux.ibm.com>
 
 	* gcc.target/powerpc/float128-lxvkq.c: New test.
 
 work053.patch014:
-2021-05-20  Michael Meissner  <meissner@linux.ibm.com>
+2021-05-25  Michael Meissner  <meissner@linux.ibm.com>
 
 	* gcc.target/powerpc/vec-splat-constant-sf.c: Update insn count.
 	* gcc.target/powerpc/vec-splat-constant-df.c: Update insn count.

[gcc(refs/users/meissner/heads/work053)] Update ChangeLog.meissner.

[Michael Meissner]

https://gcc.gnu.org/g:91c31f70de9db1966042d45a2d1c3c9821f02e57

commit 91c31f70de9db1966042d45a2d1c3c9821f02e57
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Tue May 25 01:10:03 2021 -0400

    Update ChangeLog.meissner.
    
    gcc/
    2021-05-25  Michael Meissner  <meissner@linux.ibm.com>
    
            * ChangeLog.meissner: Update.
    
    gcc/testsuite/
    2021-05-25  Michael Meissner  <meissner@linux.ibm.com>
    
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner           | 21 +++++++++++++++++++++
 gcc/testsuite/ChangeLog.meissner |  5 +++++
 2 files changed, 26 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 24868ed9207..becf9c4f039 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,24 @@
+work053.patch015:
+2021-05-25  Michael Meissner  <meissner@linux.ibm.com>
+
+	* config/rs6000/constraint.md (eQ): New constraint.
+	* config/rs6000/predicates.md (easy_fp_constant): If the constant
+	can be loaded with LXVKQ, it is easy.
+	(lxvkq_operand): New predicate.
+	* config/rs6000/rs6000-protos.h (lxvkq_constant_p): New
+	declaration.
+	* config/rs6000/rs6000-cpus.h (ISA_3_1_MASKS_SERVER): Add -mlxvkq.
+	(POWERPC_MASKS): Add -mlxvkq.
+	* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
+	support for -mlxvkq.
+	(lxvkq_constant_p): New function.
+	(rs6000_output_move_128bit): Add support for generating lxvkq.
+	(rs6000_opt_masks): Add -mlxvkq.
+	* config/rs6000/rs6000.opt (-mlxvkq): New option.
+	* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support to
+	generate lxvkq.
+	(vsx_mov<mode>_32bit): Add support to generate lxvkq.
+
 work053.patch014:
 2021-05-20  Michael Meissner  <meissner@linux.ibm.com>
 
diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner
index 3b2b31a720f..2ec74805406 100644
--- a/gcc/testsuite/ChangeLog.meissner
+++ b/gcc/testsuite/ChangeLog.meissner
@@ -1,3 +1,8 @@
+work053.patch015:
+2021-05-20  Michael Meissner  <meissner@linux.ibm.com>
+
+	* gcc.target/powerpc/float128-lxvkq.c: New test.
+
 work053.patch014:
 2021-05-20  Michael Meissner  <meissner@linux.ibm.com>

[gcc(refs/users/meissner/heads/work053)] Update ChangeLog.meissner.

[Michael Meissner]

https://gcc.gnu.org/g:12f082d8121490a8d5a4a1397e169adfe38fc27f

commit 12f082d8121490a8d5a4a1397e169adfe38fc27f
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu May 20 10:38:40 2021 -0400

    Update ChangeLog.meissner.
    
    gcc/
    2021-05-20  Michael Meissner  <meissner@linux.ibm.com>
    
            * ChangeLog.meissner: Update.
    
    gcc/testsuite/
    2021-05-20  Michael Meissner  <meissner@linux.ibm.com>
    
            * ChangeLog.meissner: Update.
    
    libgcc/
    2021-05-20  Michael Meissner  <meissner@linux.ibm.com>
    
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner           | 204 +++++++++++++++++++++++++++++++++++++++
 gcc/testsuite/ChangeLog.meissner | 125 ++++++++++++++++++++++++
 libgcc/ChangeLog.meissner        |   6 ++
 3 files changed, 335 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index d9f282e5ebb..24868ed9207 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,207 @@
+work053.patch014:
+2021-05-20  Michael Meissner  <meissner@linux.ibm.com>
+
+	* config/rs6000/constraint.md (eD): New constraint.
+	* config/rs6000/predicates.md (easy_fp_constant): If the constant
+	can be loaded with XXSPLTI32DX, it is easy.
+	(xxsplti32dx_operand): New predicate.
+	(easy_vector_constant): If the constant can be loaded with
+	XXSPLTI32DX, it is easy.
+	* config/rs6000/rs6000-protos.h (xxsplti32dx_constant_p): New
+	declaration.
+	* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
+	support for -mxxsplti32dx.
+	(xxsplti32dx_constant_float_p): New helper function.
+	(xxsplti32dx_constant_p): New function.
+	(output_vec_const_move): If the operand can be loaded with
+	XXSPLTI32DX, split it.
+	(rs6000_opt_masks): Add -mxxsplti32dx.
+	* config/rs6000/rs6000.md (movsf_hardfloat): Add support for
+	constants loaded with XXSPLTI32DX.
+	(mov<mode>_hardfloat32, FMOVE64 iterator):  Add support for
+	constants loaded with XXSPLTI32DX.
+	(mov<mode>_hardfloat64, FMOVE64 iterator):  Add support for
+	constants loaded with XXSPLTI32DX.
+	* config/rs6000/rs6000.opt (-mxxsplti32dx): New option.
+	* config/rs6000/vsx.md (UNSPEC_XXSPLTI32DX_CONST): New unspec.
+	(XXSPLTI32DX): New mode iterator.
+	(xxsplti32dx_<mode>): New insn and splitter for XXSPLTI32DX.
+	(xxsplti32dx_<mode>_first): New insn.
+	(xxsplti32dx_<mode>_second): New insn.
+
+work053.patch013:
+2021-05-20  Michael Meissner  <meissner@linux.ibm.com>
+
+	* config/rs6000/constraints.md (eF): New constraint.
+	* config/rs6000/predicates.md (easy_fp_constant): If we can load
+	the scalar constant with XXSPLTIDP, the floating point constant is
+	easy.
+	(xxspltidp_operand): New predicate.
+	(easy_vector_constant): If we can generate XXSPLTIDP, mark the
+	vector constant as easy.
+	* config/rs6000/rs6000-cpus.def (OTHER_POWER10_MASKS): Add
+	-mxxspltidp support.
+	(POWERPC_MASKS): Add -mxxspltidp support.
+	* config/rs6000/rs6000-protos.h (xxspltidp_constant_p): New
+	declaration.
+	* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
+	-mxxspltidp support.
+	(const_vector_element_all_same): New function.
+	(xxspltidp_constant_p): New function.
+	(output_vec_const_move): Add support for XXSPLTIDP.
+	(rs6000_opt_masks): Add -mxxspltidp support.
+	(rs6000_emit_xxspltidp_v2df): Change function to implement the
+	XXSPLTIDP instruction.
+	* config/rs6000/rs6000.md (movsf_hardfloat): Add XXSPLTIDP
+	support.
+	(mov<mode>_hardfloat32, FMOVE64 iterator): Add XXSPLTIDP support.
+	(mov<mode>_hardfloat64, FMOVE64 iterator): Add XXSPLTIDP support.
+	* config/rs6000/rs6000.opt (-mxxspltidp): New switch.
+	* config/rs6000/vsx.md (UNSPEC_XXSPLTIDP): Rename UNSPEC_XXSPLTID
+	to UNSPEC_XXSPLTIDP to match the instruction.
+	(xxspltidp_v2df): Use 'use' for the expand arguments, instead of
+	writing out an insn.
+	(xxspltidp_v2df_inst): Delete.
+	(XXSPLTIDP): New mode iterator.
+	(xxspltidp_<mode>_internal1): New define_insn_and_split.
+	(xxspltidp_<mode>_internal2): New define_insn.
+
+work053.patch012:
+2021-05-20  Michael Meissner  <meissner@linux.ibm.com>
+
+	* config/rs6000/predicates.md (xxspltiw_operand): New predicate.
+	(easy_vector_constant): If we can use XXSPLTIW, the vector
+	constant is easy.
+	* config/rs6000/rs6000-cpus.def (ISA_3_1_MASKS_SERVER): Add
+	-mxxspltiw support.
+	(POWERPC_MASKS): Add -mxxspltiw support.
+	* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
+	-mxxspltiw support.
+	(xxspltib_constant_p): If we can generate XXSPLTIW, don't generate
+	a XXSPLTIB and an extend instruction.
+	(output_vec_const_move): Add support for loading up vector
+	constants with XXSPLTIW.
+	(rs6000_opt_masks): Add -mxxspltiw.
+	* config/rs6000/rs6000.h (SIGN_EXTEND_8BIT): New macro.
+	(SIGN_EXTEND_16BIT): New macro.
+	(SIGN_EXTEND_32BIT): New macro.
+	* config/rs6000/rs6000.opt (-mxxspltiw): New debug switch.
+	* config/rs6000/vsx.md (UNSPEC_XXSPLTIW): Delete.
+	(xxspltiw_v8hi): New insn.
+	(xxspltiw_v4si): Rewrite to generate a vector constant.
+	(xxspltiw_v4sf): Rewrite to generate a vector constant.
+	(xxspltiw_v4si_inst): Delete.
+	(xxspltiw_v4sf_inst): Delete.
+	(xxspltiw_v8hi_dup): New insn.
+	(xxspltiw_v4si_dup): New insn.
+	(xxspltiw_v4sf_dup): New insn.
+	(XXSPLTIW): New mode iterator.
+	(XXSPLTIW splitter): New insn splitter for XXSPLTIW.
+
+work053.patch008:
+2021-05-18  Michael Meissner  <meissner@linux.ibm.com>
+
+	* config/rs6000/vsx.md (xxeval): Use register_predicate instead of
+	altivec_register_predicate.
+
+work053.patch007:
+2021-05-18  Michael Meissner  <meissner@linux.ibm.com>
+
+	* config/rs6000/altivec.md (UNSPEC_XXEVAL): Move to vsx.md.
+	(UNSPEC_XXSPLTIW): Move to vsx.md.
+	(UNSPEC_XXSPLTID): Move to vsx.md.
+	(UNSPEC_XXSPLTI32DX): Move to vsx.md.
+	(UNSPEC_XXBLEND): Move to vsx.md.
+	(UNSPEC_XXPERMX): Move to vsx.md.
+	(VM3): Move to vsx.md.
+	(VM3_char): Move to vsx.md.
+	(xxspltiw_v4si): Move to vsx.md.
+	(xxspltiw_v4sf): Move to vsx.md.
+	(xxspltiw_v4sf_inst): Move to vsx.md.
+	(xxspltidp_v2df): Move to vsx.md.
+	(xxspltidp_v2df_inst): Move to vsx.md.
+	(xxsplti32dx_v4si_inst): Move to vsx.md.
+	(xxsplti32dx_v4sf): Move to vsx.md.
+	(xxsplti32dx_v4sf_inst): Move to vsx.md.
+	(xxblend_<mode>): Move to vsx.md.
+	(xxpermx): Move to vsx.md.
+	(xxpermx_inst): Move to vsx.md.
+	* config/rs6000/vsx.md (UNSPEC_XXEVAL): Move from altivec.md.
+	(UNSPEC_XXSPLTIW): Move from altivec.md.
+	(UNSPEC_XXSPLTID): Move from altivec.md.
+	(UNSPEC_XXSPLTI32DX): Move from altivec.md.
+	(UNSPEC_XXBLEND): Move from altivec.md.
+	(UNSPEC_XXPERMX): Move from altivec.md.
+	(VM3): Move from altivec.md.
+	(VM3_char): Move from altivec.md.
+	(xxspltiw_v4si): Move from altivec.md.
+	(xxspltiw_v4sf): Move from altivec.md.
+	(xxspltiw_v4sf_inst): Move from altivec.md.
+	(xxspltidp_v2df): Move from altivec.md.
+	(xxspltidp_v2df_inst): Move from altivec.md.
+	(xxsplti32dx_v4si_inst): Move from altivec.md.
+	(xxsplti32dx_v4sf): Move from altivec.md.
+	(xxsplti32dx_v4sf_inst): Move from altivec.md.
+	(xxblend_<mode>): Move from altivec.md.
+	(xxpermx): Move from altivec.md.
+	(xxpermx_inst): Move from altivec.md.
+
+work053.patch006:
+2021-05-17  Michael Meissner  <meissner@linux.ibm.com>
+
+	* config.gcc (powerpc*-*-*, rs6000-*-*): Do not set
+	LINK_OS_EXTRA_SPEC664 for the Advance Toolchain.  Continue to set
+	LINK_OS_EXTRA_SPEC32.
+
+work053.patch005:
+2021-05-18  Michael Meissner  <meissner@linux.ibm.com>
+
+	* config/rs6000/rs6000-protos.h (rs6000_const_f32_to_i32): Change
+	return type to long.
+	* config/rs6000/rs6000.c (rs6000_const_f32_to_i32): Change return
+	type to long.
+
+work053.patch004:
+2021-05-18  Michael Meissner  <meissner@linux.ibm.com>
+
+	* config/rs6000/rs6000-builtin.def (BU_IBM128_2): Rename
+	RS6000_BTM_IBM128 from RS6000_BTM_FLOAT128.
+	* config/rs6000/rs6000-call.c (rs6000_invalid_builtin): Update
+	error message for __ibm128 built-in functions.
+	(rs6000_init_builtins): Create the __ibm128 keyword on older
+	systems where long double uses the IBM extended double format,
+	even if they don't support IEEE 128-bit floating point.
+	* config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Rename
+	RS6000_BTM_IBM128 from RS6000_BTM_FLOAT128.
+	(rs6000_builtin_mask_names): Rename RS6000_BTM_IBM128 from
+	RS6000_BTM_FLOAT128.
+	* config/rs6000/rs6000.h (TARGET_IBM128): New macro.
+	(RS6000_BTM_IBM128): Rename from RS6000_BTM_FLOAT128.
+	(RS6000_BTM_COMMON): Rename RS6000_BTM_IBM128 from
+	RS6000_BTM_FLOAT128.
+
+work053.patch002:
+2021-05-18 Michael Meissner  <meissner@linux.ibm.com>
+
+        * config/rs6000/rs6000.c (rs6000_maybe_emit_fp_cmove): Add IEEE
+	128-bit floating point conditional move support.
+	(have_compare_and_set_mask): Add IEEE 128-bit floating point
+	types.
+	* config/rs6000/rs6000.md (mov<mode>cc, IEEE128 iterator): New insn.
+	(mov<mode>cc_p10, IEEE128 iterator): New insn.
+	(mov<mode>cc_invert_p10, IEEE128 iterator): New insn.
+	(fpmask<mode>, IEEE128 iterator): New insn.
+	(xxsel<mode>, IEEE128 iterator): New insn.
+
+work053.patch001:
+2021-05-18  Michael Meissner  <meissner@linux.ibm.com>
+
+	* config/rs6000/rs6000.c (rs6000_emit_minmax): Add support for ISA
+	3.1   IEEE   128-bit   floating  point   xsmaxcqp   and   xsmincqp
+	instructions.
+	* config/rs6000/rs6000.md (s<minmax><mode>3, IEEE128 iterator):
+	New insns.
+
 2021-05-17   Michael Meissner  <meissner@linux.ibm.com>
 
 	Clone branch
diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner
index d9f282e5ebb..3b2b31a720f 100644
--- a/gcc/testsuite/ChangeLog.meissner
+++ b/gcc/testsuite/ChangeLog.meissner
@@ -1,3 +1,128 @@
+work053.patch014:
+2021-05-20  Michael Meissner  <meissner@linux.ibm.com>
+
+	* gcc.target/powerpc/vec-splat-constant-sf.c: Update insn count.
+	* gcc.target/powerpc/vec-splat-constant-df.c: Update insn count.
+	* gcc.target/powerpc/vec-splat-constant-v2df.c: Update insn
+	count.
+
+work053.patch013:
+2021-05-20  Michael Meissner  <meissner@linux.ibm.com>
+
+	* gcc.target/powerpc/vec-splat-constant-sf.c: New test.
+	* gcc.target/powerpc/vec-splat-constant-df.c: New test.
+	* gcc.target/powerpc/vec-splat-constant-v2df.c: New test.
+
+work053.patch012:
+2021-05-20  Michael Meissner  <meissner@linux.ibm.com>
+
+	* gcc.target/powerpc/pr86731-fwrapv.c: Turn off power10 code
+	generation.
+	* gcc.target/powerpc/vec-splati-runnable.c: Update insn counts.
+	* gcc.target/powerpc/vec-splat-constant-v4sf.c: New test.
+	* gcc.target/powerpc/vec-splat-constant-v4si.c: New test.
+	* gcc.target/powerpc/vec-splat-constant-v8hi.c: New test.
+
+work053.patch011:
+2021-05-18  Michael Meissner  <meissner@linux.ibm.com>
+
+	PR testsuite/100166
+	* gcc.dg/pr56727-2.c: Add support for PC-relative calls.
+	* gcc.target/powerpc/fold-vec-div-longlong.c:
+	* gcc.target/powerpc/fold-vec-mult-longlong.c: Disable power10
+	code generation.
+	* gcc.target/powerpc/ppc-eq0-1.c: Add support for the setbc
+	instruction.
+	* gcc.target/powerpc/ppc-ne0-1.c: Disable power10 code
+	generation.
+
+work053.patch010:
+2021-05-18  Michael Meissner  <meissner@linux.ibm.com>
+
+	PR testsuite/100166
+	* gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c:
+	* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c:
+	* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-double.c:
+	* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-float.c:
+	* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-int.c:
+	* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-longlong.c:
+	* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-short.c:
+	* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-char.c:
+	* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-double.c:
+	* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-float.c:
+	* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-int.c:
+	* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-longlong.c:
+	* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-short.c:
+	* gcc.target/powerpc/fold-vec-load-vec_xl-char.c:
+	* gcc.target/powerpc/fold-vec-load-vec_xl-double.c:
+	* gcc.target/powerpc/fold-vec-load-vec_xl-float.c:
+	* gcc.target/powerpc/fold-vec-load-vec_xl-int.c:
+	* gcc.target/powerpc/fold-vec-load-vec_xl-longlong.c:
+	* gcc.target/powerpc/fold-vec-load-vec_xl-short.c:
+	* gcc.target/powerpc/fold-vec-splat-floatdouble.c:
+	* gcc.target/powerpc/fold-vec-splat-longlong.c:
+	* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-char.c:
+	* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-double.c:
+	* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-float.c:
+	* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-int.c:
+	* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-longlong.c:
+	* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-short.c:
+	* gcc.target/powerpc/fold-vec-store-vec_vsx_st-char.c:
+	* gcc.target/powerpc/fold-vec-store-vec_vsx_st-double.c:
+	* gcc.target/powerpc/fold-vec-store-vec_vsx_st-float.c:
+	* gcc.target/powerpc/fold-vec-store-vec_vsx_st-int.c:
+	* gcc.target/powerpc/fold-vec-store-vec_vsx_st-longlong.c:
+	* gcc.target/powerpc/fold-vec-store-vec_vsx_st-short.c:
+	* gcc.target/powerpc/fold-vec-store-vec_xst-char.c:
+	* gcc.target/powerpc/fold-vec-store-vec_xst-double.c:
+	* gcc.target/powerpc/fold-vec-store-vec_xst-float.c:
+	* gcc.target/powerpc/fold-vec-store-vec_xst-int.c:
+	* gcc.target/powerpc/fold-vec-store-vec_xst-longlong.c:
+	* gcc.target/powerpc/fold-vec-store-vec_xst-short.c:
+	* gcc.target/powerpc/lvsl-lvsr.c:
+	* gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c:
+	Update insn counts to account for power10 prefixed loads and
+	stores.
+
+work053.patch009:
+2021-05-18  Michael Meissner  <meissner@linux.ibm.com>
+
+	* gcc.target/powerpc/vec-splati-runnable.c: Run test with -O2
+	optimization.  Do not check what XXSPLTIDP generates if the value
+	is undefined.
+
+work053.patch003:
+2021-05-18  Michael Meissner  <meissner@linux.ibm.com>
+
+	PR target/70117
+	* gcc.target/powerpc/pr70117.c: Force the long double type to use
+	the IBM 128-bit format.
+	* c-c++-common/dfp/convert-bfp-11.c: Force using IBM 128-bit long
+	double.  Remove check for 64-bit long double.
+	* lib/target-supports.exp
+	(add_options_for_ppc_long_double_override_ibm128): New function.
+	(check_effective_target_ppc_long_double_override_ibm128): New
+	function.
+	(add_options_for_ppc_long_double_override_ieee128): New function.
+	(check_effective_target_ppc_long_double_override_ieee128): New
+	function.
+	(add_options_for_ppc_long_double_override_64bit): New function.
+	(check_effective_target_ppc_long_double_override_64bit): New
+	function.
+
+work053.patch002:
+2021-05-18  Michael Meissner  <meissner@linux.ibm.com>
+
+        * gcc.target/powerpc/float128-cmove.c: New test.
+        * gcc.target/powerpc/float128-minmax-3.c: New test.
+
+work053.patch001:
+2021-05-18  Michael Meissner  <meissner@linux.ibm.com>
+
+	* gcc.target/powerpc/float128-minmax-2.c: New test.
+	* gcc.target/powerpc/float128-minmax.c: Turn off power10 code
+	generation.
+
 2021-05-17   Michael Meissner  <meissner@linux.ibm.com>
 
 	Clone branch
diff --git a/libgcc/ChangeLog.meissner b/libgcc/ChangeLog.meissner
index d9f282e5ebb..baf3a147623 100644
--- a/libgcc/ChangeLog.meissner
+++ b/libgcc/ChangeLog.meissner
@@ -1,3 +1,9 @@
+work053.patch004:
+2021-05-18  Michael Meissner  <meissner@linux.ibm.com>
+
+	* config/rs6000/ibm-ldouble.c (pack_ldouble): Use
+	__builtin_pack_ibm128 instead of __builtin_pack_longdouble.
+
 2021-05-17   Michael Meissner  <meissner@linux.ibm.com>
 
 	Clone branch