[gcc(refs/users/meissner/heads/work056)] Split loading DImode integers early.

[gcc(refs/users/meissner/heads/work056)] Split loading DImode integers early.

[Michael Meissner]

https://gcc.gnu.org/g:1f597e0024c1b30a5d3a0c77491f464d7235d53a

commit 1f597e0024c1b30a5d3a0c77491f464d7235d53a
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Tue Jun 22 21:23:17 2021 -0400

    Split loading DImode integers early.
    
    gcc/
    2021-06-22  Michael Meissner  <meissner@linux.ibm.com>
    
            * config/rs6000/rs6000.md (load DImode constant spliters): Use
            int_reg_operand instead of int_reg_operand_not_pseudo so loading
            up large DImode constants happens before register allocation.

Diff:
---
 gcc/config/rs6000/rs6000.md | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 3ba0beaee32..4160efa36cc 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -9404,29 +9404,32 @@
 ; Some DImode loads are best done as a load of -1 followed by a mask
 ; instruction.
 (define_split
-  [(set (match_operand:DI 0 "int_reg_operand_not_pseudo")
+  [(set (match_operand:DI 0 "int_reg_operand")
 	(match_operand:DI 1 "const_int_operand"))]
   "TARGET_POWERPC64
    && num_insns_constant (operands[1], DImode) > 1
    && !IN_RANGE (INTVAL (operands[1]), -0x80000000, 0xffffffff)
    && rs6000_is_valid_and_mask (operands[1], DImode)"
-  [(set (match_dup 0)
+  [(set (match_dup 2)
 	(const_int -1))
    (set (match_dup 0)
-	(and:DI (match_dup 0)
+	(and:DI (match_dup 2)
 		(match_dup 1)))]
-  "")
+{
+  operands[2] = ((can_create_pseudo_p ())
+		 ? gen_reg_rtx (DImode)
+		 : operands[0]);
+})
 
 ;; Split a load of a large constant into the appropriate five-instruction
 ;; sequence.  Handle anything in a constant number of insns.
 ;; When non-easy constants can go in the TOC, this should use
 ;; easy_fp_constant predicate.
 (define_split
-  [(set (match_operand:DI 0 "int_reg_operand_not_pseudo")
+  [(set (match_operand:DI 0 "int_reg_operand")
 	(match_operand:DI 1 "const_int_operand"))]
   "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
-  [(set (match_dup 0) (match_dup 2))
-   (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
+  [(pc)]
 {
   if (rs6000_emit_set_const (operands[0], operands[1]))
     DONE;
@@ -9435,11 +9438,10 @@
 })
 
 (define_split
-  [(set (match_operand:DI 0 "int_reg_operand_not_pseudo")
+  [(set (match_operand:DI 0 "int_reg_operand")
 	(match_operand:DI 1 "const_scalar_int_operand"))]
   "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
-  [(set (match_dup 0) (match_dup 2))
-   (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
+  [(pc)]
 {
   if (rs6000_emit_set_const (operands[0], operands[1]))
     DONE;