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* [gcc(refs/users/wschmidt/heads/builtins10)] rs6000: Add power7 and power7-64 builtins
@ 2021-06-25 16:17 William Schmidt
0 siblings, 0 replies; 7+ messages in thread
From: William Schmidt @ 2021-06-25 16:17 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:c1d9af359def7ca2eb8dba3f122259bf49179aac
commit c1d9af359def7ca2eb8dba3f122259bf49179aac
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Fri Apr 2 16:48:36 2021 -0500
rs6000: Add power7 and power7-64 builtins
2021-04-02 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/rs6000-builtin-new.def: Add power7 and power7-64
stanzas.
Diff:
---
gcc/config/rs6000/rs6000-builtin-new.def | 39 ++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index ca694be1ac3..bffce52ee47 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -1957,3 +1957,42 @@
const vsll __builtin_vsx_xxspltd_2di (vsll, const int<1>);
XXSPLTD_V2DI vsx_xxspltd_v2di {}
+
+
+; Power7 builtins (ISA 2.06).
+[power7]
+ const unsigned int __builtin_addg6s (unsigned int, unsigned int);
+ ADDG6S addg6s {}
+
+ const signed long __builtin_bpermd (signed long, signed long);
+ BPERMD bpermd_di {}
+
+ const unsigned int __builtin_cbcdtd (unsigned int);
+ CBCDTD cbcdtd {}
+
+ const unsigned int __builtin_cdtbcd (unsigned int);
+ CDTBCD cdtbcd {}
+
+ const signed int __builtin_divwe (signed int, signed int);
+ DIVWE dive_si {}
+
+ const unsigned int __builtin_divweu (unsigned int, unsigned int);
+ DIVWEU diveu_si {}
+
+ const vsq __builtin_pack_vector_int128 (unsigned long long, unsigned long long);
+ PACK_V1TI packv1ti {}
+
+ void __builtin_ppc_speculation_barrier ();
+ SPECBARR speculation_barrier {}
+
+ const unsigned long __builtin_unpack_vector_int128 (vsq, const int<1>);
+ UNPACK_V1TI unpackv1ti {}
+
+
+; Power7 builtins requiring 64-bit GPRs (even with 32-bit addressing).
+[power7-64]
+ const signed long long __builtin_divde (signed long long, signed long long);
+ DIVDE dive_di {}
+
+ const unsigned long long __builtin_divdeu (unsigned long long, unsigned long long);
+ DIVDEU diveu_di {}
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins10)] rs6000: Add power7 and power7-64 builtins
@ 2021-07-29 14:45 William Schmidt
0 siblings, 0 replies; 7+ messages in thread
From: William Schmidt @ 2021-07-29 14:45 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:a448168cdd6e5aa192c650119490d81aa1d48a19
commit a448168cdd6e5aa192c650119490d81aa1d48a19
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Fri Apr 2 16:48:36 2021 -0500
rs6000: Add power7 and power7-64 builtins
2021-04-02 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/rs6000-builtin-new.def: Add power7 and power7-64
stanzas.
Diff:
---
gcc/config/rs6000/rs6000-builtin-new.def | 39 ++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index ca694be1ac3..bffce52ee47 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -1957,3 +1957,42 @@
const vsll __builtin_vsx_xxspltd_2di (vsll, const int<1>);
XXSPLTD_V2DI vsx_xxspltd_v2di {}
+
+
+; Power7 builtins (ISA 2.06).
+[power7]
+ const unsigned int __builtin_addg6s (unsigned int, unsigned int);
+ ADDG6S addg6s {}
+
+ const signed long __builtin_bpermd (signed long, signed long);
+ BPERMD bpermd_di {}
+
+ const unsigned int __builtin_cbcdtd (unsigned int);
+ CBCDTD cbcdtd {}
+
+ const unsigned int __builtin_cdtbcd (unsigned int);
+ CDTBCD cdtbcd {}
+
+ const signed int __builtin_divwe (signed int, signed int);
+ DIVWE dive_si {}
+
+ const unsigned int __builtin_divweu (unsigned int, unsigned int);
+ DIVWEU diveu_si {}
+
+ const vsq __builtin_pack_vector_int128 (unsigned long long, unsigned long long);
+ PACK_V1TI packv1ti {}
+
+ void __builtin_ppc_speculation_barrier ();
+ SPECBARR speculation_barrier {}
+
+ const unsigned long __builtin_unpack_vector_int128 (vsq, const int<1>);
+ UNPACK_V1TI unpackv1ti {}
+
+
+; Power7 builtins requiring 64-bit GPRs (even with 32-bit addressing).
+[power7-64]
+ const signed long long __builtin_divde (signed long long, signed long long);
+ DIVDE dive_di {}
+
+ const unsigned long long __builtin_divdeu (unsigned long long, unsigned long long);
+ DIVDEU diveu_di {}
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins10)] rs6000: Add power7 and power7-64 builtins
@ 2021-06-15 17:18 William Schmidt
0 siblings, 0 replies; 7+ messages in thread
From: William Schmidt @ 2021-06-15 17:18 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:51b432be1e9d3ee5b0e0a51df8b2c4ed336eb5ff
commit 51b432be1e9d3ee5b0e0a51df8b2c4ed336eb5ff
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Fri Apr 2 16:48:36 2021 -0500
rs6000: Add power7 and power7-64 builtins
2021-04-02 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/rs6000-builtin-new.def: Add power7 and power7-64
stanzas.
Diff:
---
gcc/config/rs6000/rs6000-builtin-new.def | 39 ++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index ca694be1ac3..bffce52ee47 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -1957,3 +1957,42 @@
const vsll __builtin_vsx_xxspltd_2di (vsll, const int<1>);
XXSPLTD_V2DI vsx_xxspltd_v2di {}
+
+
+; Power7 builtins (ISA 2.06).
+[power7]
+ const unsigned int __builtin_addg6s (unsigned int, unsigned int);
+ ADDG6S addg6s {}
+
+ const signed long __builtin_bpermd (signed long, signed long);
+ BPERMD bpermd_di {}
+
+ const unsigned int __builtin_cbcdtd (unsigned int);
+ CBCDTD cbcdtd {}
+
+ const unsigned int __builtin_cdtbcd (unsigned int);
+ CDTBCD cdtbcd {}
+
+ const signed int __builtin_divwe (signed int, signed int);
+ DIVWE dive_si {}
+
+ const unsigned int __builtin_divweu (unsigned int, unsigned int);
+ DIVWEU diveu_si {}
+
+ const vsq __builtin_pack_vector_int128 (unsigned long long, unsigned long long);
+ PACK_V1TI packv1ti {}
+
+ void __builtin_ppc_speculation_barrier ();
+ SPECBARR speculation_barrier {}
+
+ const unsigned long __builtin_unpack_vector_int128 (vsq, const int<1>);
+ UNPACK_V1TI unpackv1ti {}
+
+
+; Power7 builtins requiring 64-bit GPRs (even with 32-bit addressing).
+[power7-64]
+ const signed long long __builtin_divde (signed long long, signed long long);
+ DIVDE dive_di {}
+
+ const unsigned long long __builtin_divdeu (unsigned long long, unsigned long long);
+ DIVDEU diveu_di {}
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins10)] rs6000: Add power7 and power7-64 builtins
@ 2021-04-26 20:50 William Schmidt
0 siblings, 0 replies; 7+ messages in thread
From: William Schmidt @ 2021-04-26 20:50 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:f70d8f93775ad606d5f752a0827258aeb95db8a0
commit f70d8f93775ad606d5f752a0827258aeb95db8a0
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Fri Apr 2 16:48:36 2021 -0500
rs6000: Add power7 and power7-64 builtins
2021-04-02 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/rs6000-builtin-new.def: Add power7 and power7-64
stanzas.
Diff:
---
gcc/config/rs6000/rs6000-builtin-new.def | 39 ++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 0dc2cd2c99e..7ea8598bf16 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -1957,3 +1957,42 @@
const vsll __builtin_vsx_xxspltd_2di (vsll, const int<1>);
XXSPLTD_V2DI vsx_xxspltd_v2di {}
+
+
+; Power7 builtins (ISA 2.06).
+[power7]
+ const unsigned int __builtin_addg6s (unsigned int, unsigned int);
+ ADDG6S addg6s {}
+
+ const signed long __builtin_bpermd (signed long, signed long);
+ BPERMD bpermd_di {}
+
+ const unsigned int __builtin_cbcdtd (unsigned int);
+ CBCDTD cbcdtd {}
+
+ const unsigned int __builtin_cdtbcd (unsigned int);
+ CDTBCD cdtbcd {}
+
+ const signed int __builtin_divwe (signed int, signed int);
+ DIVWE dive_si {}
+
+ const unsigned int __builtin_divweu (unsigned int, unsigned int);
+ DIVWEU diveu_si {}
+
+ const vsq __builtin_pack_vector_int128 (unsigned long long, unsigned long long);
+ PACK_V1TI packv1ti {}
+
+ void __builtin_ppc_speculation_barrier ();
+ SPECBARR speculation_barrier {}
+
+ const unsigned long __builtin_unpack_vector_int128 (vsq, const int<1>);
+ UNPACK_V1TI unpackv1ti {}
+
+
+; Power7 builtins requiring 64-bit GPRs (even with 32-bit addressing).
+[power7-64]
+ const signed long long __builtin_divde (signed long long, signed long long);
+ DIVDE dive_di {}
+
+ const unsigned long long __builtin_divdeu (unsigned long long, unsigned long long);
+ DIVDEU diveu_di {}
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins10)] rs6000: Add power7 and power7-64 builtins
@ 2021-04-02 22:11 William Schmidt
0 siblings, 0 replies; 7+ messages in thread
From: William Schmidt @ 2021-04-02 22:11 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:0b81e6ba9eb463633628fee02d606e63ef2409a3
commit 0b81e6ba9eb463633628fee02d606e63ef2409a3
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Fri Apr 2 16:48:36 2021 -0500
rs6000: Add power7 and power7-64 builtins
2021-04-02 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/rs6000-builtin-new.def: Add power7 and power7-64
stanzas.
Diff:
---
gcc/config/rs6000/rs6000-builtin-new.def | 39 ++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 0dc2cd2c99e..7ea8598bf16 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -1957,3 +1957,42 @@
const vsll __builtin_vsx_xxspltd_2di (vsll, const int<1>);
XXSPLTD_V2DI vsx_xxspltd_v2di {}
+
+
+; Power7 builtins (ISA 2.06).
+[power7]
+ const unsigned int __builtin_addg6s (unsigned int, unsigned int);
+ ADDG6S addg6s {}
+
+ const signed long __builtin_bpermd (signed long, signed long);
+ BPERMD bpermd_di {}
+
+ const unsigned int __builtin_cbcdtd (unsigned int);
+ CBCDTD cbcdtd {}
+
+ const unsigned int __builtin_cdtbcd (unsigned int);
+ CDTBCD cdtbcd {}
+
+ const signed int __builtin_divwe (signed int, signed int);
+ DIVWE dive_si {}
+
+ const unsigned int __builtin_divweu (unsigned int, unsigned int);
+ DIVWEU diveu_si {}
+
+ const vsq __builtin_pack_vector_int128 (unsigned long long, unsigned long long);
+ PACK_V1TI packv1ti {}
+
+ void __builtin_ppc_speculation_barrier ();
+ SPECBARR speculation_barrier {}
+
+ const unsigned long __builtin_unpack_vector_int128 (vsq, const int<1>);
+ UNPACK_V1TI unpackv1ti {}
+
+
+; Power7 builtins requiring 64-bit GPRs (even with 32-bit addressing).
+[power7-64]
+ const signed long long __builtin_divde (signed long long, signed long long);
+ DIVDE dive_di {}
+
+ const unsigned long long __builtin_divdeu (unsigned long long, unsigned long long);
+ DIVDEU diveu_di {}
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins10)] rs6000: Add power7 and power7-64 builtins
@ 2021-04-01 19:49 William Schmidt
0 siblings, 0 replies; 7+ messages in thread
From: William Schmidt @ 2021-04-01 19:49 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:aa8c6807bad7c597d0530cfe7913d88816c9224f
commit aa8c6807bad7c597d0530cfe7913d88816c9224f
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Thu Apr 1 13:52:51 2021 -0500
rs6000: Add power7 and power7-64 builtins
2021-04-01 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/rs6000-builtin-new.def: Add power7 and power7-64
stanzas.
Diff:
---
gcc/config/rs6000/rs6000-builtin-new.def | 42 ++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 43e4f79ddb8..4209fd105aa 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -1956,3 +1956,45 @@
const vsll __builtin_vsx_xxspltd_2di (vsll, const int<1>);
XXSPLTD_V2DI vsx_xxspltd_v2di {}
+
+
+; Power7 builtins (ISA 2.06).
+[power7]
+ const unsigned int __builtin_addg6s (unsigned int, unsigned int);
+ ADDG6S addg6s {}
+
+; This one requires special handling at expand time; it should be
+; expanded to bperm_di in 64-bit mode and bpermd_si in 32-bit mode.
+; Use of "long" for this builtin is sanctioned.
+ const signed long __builtin_bpermd (signed long, signed long);
+ BPERMD bpermd_di {}
+
+ const unsigned int __builtin_cbcdtd (unsigned int);
+ CBCDTD cbcdtd {}
+
+ const unsigned int __builtin_cdtbcd (unsigned int);
+ CDTBCD cdtbcd {}
+
+ const signed int __builtin_divwe (signed int, signed int);
+ DIVWE dive_si {}
+
+ const unsigned int __builtin_divweu (unsigned int, unsigned int);
+ DIVWEU diveu_si {}
+
+ const vsq __builtin_pack_vector_int128 (unsigned long long, unsigned long long);
+ PACK_V1TI packv1ti {}
+
+ void __builtin_ppc_speculation_barrier ();
+ SPECBARR speculation_barrier {}
+
+ const unsigned long __builtin_unpack_vector_int128 (vsq, const int<1>);
+ UNPACK_V1TI unpackv1ti {}
+
+
+; Power7 builtins requiring 64-bit GPRs (even with 32-bit addressing).
+[power7-64]
+ const signed long long __builtin_divde (signed long long, signed long long);
+ DIVDE dive_di {}
+
+ const unsigned long long __builtin_divdeu (unsigned long long, unsigned long long);
+ DIVDEU diveu_di {}
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins10)] rs6000: Add power7 and power7-64 builtins
@ 2021-03-25 15:46 William Schmidt
0 siblings, 0 replies; 7+ messages in thread
From: William Schmidt @ 2021-03-25 15:46 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:898b6a5da3a459392983111c7f4e864faed1f759
commit 898b6a5da3a459392983111c7f4e864faed1f759
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Thu Mar 4 13:05:45 2021 -0600
rs6000: Add power7 and power7-64 builtins
2021-03-04 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/rs6000-builtin-new.def: Add power7 and power7-64
stanzas.
Diff:
---
gcc/config/rs6000/rs6000-builtin-new.def | 42 ++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index b0570b4d316..50db3e49b3c 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -1971,3 +1971,45 @@
const vsll __builtin_vsx_xxspltd_2di (vsll, const int<1>);
XXSPLTD_V2DI vsx_xxspltd_v2di {}
+
+
+; Power7 builtins (ISA 2.06).
+[power7]
+ const unsigned int __builtin_addg6s (unsigned int, unsigned int);
+ ADDG6S addg6s {}
+
+; This one requires special handling at expand time; it should be
+; expanded to bperm_di in 64-bit mode and bpermd_si in 32-bit mode.
+; Use of "long" for this builtin is sanctioned.
+ const signed long __builtin_bpermd (signed long, signed long);
+ BPERMD bpermd_di {}
+
+ const unsigned int __builtin_cbcdtd (unsigned int);
+ CBCDTD cbcdtd {}
+
+ const unsigned int __builtin_cdtbcd (unsigned int);
+ CDTBCD cdtbcd {}
+
+ const signed int __builtin_divwe (signed int, signed int);
+ DIVWE dive_si {}
+
+ const unsigned int __builtin_divweu (unsigned int, unsigned int);
+ DIVWEU diveu_si {}
+
+ const vsq __builtin_pack_vector_int128 (unsigned long long, unsigned long long);
+ PACK_V1TI packv1ti {}
+
+ void __builtin_ppc_speculation_barrier ();
+ SPECBARR speculation_barrier {}
+
+ const unsigned long long __builtin_unpack_vector_int128 (vsq, const int<1>);
+ UNPACK_V1TI unpackv1ti {}
+
+
+; Power7 builtins requiring 64-bit GPRs (even with 32-bit addressing).
+[power7-64]
+ const signed long long __builtin_divde (signed long long, signed long long);
+ DIVDE dive_di {}
+
+ const unsigned long long __builtin_divdeu (unsigned long long, unsigned long long);
+ DIVDEU diveu_di {}
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2021-07-29 14:45 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
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