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* [gcc(refs/users/meissner/heads/work058)] Generate 128-bit divide/modulus.
@ 2021-07-04 12:45 Michael Meissner
0 siblings, 0 replies; 3+ messages in thread
From: Michael Meissner @ 2021-07-04 12:45 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:1d823c05c93c5ae822c4c6ee6f8011f604475648
commit 1d823c05c93c5ae822c4c6ee6f8011f604475648
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Sun Jul 4 08:45:08 2021 -0400
Generate 128-bit divide/modulus.
This patch adds support for the VDIVSQ, VDIVUQ, VMODSQ, and VMODUQ
instructions to do 128-bit arithmetic.
2021-07-04 Michael Meissner <meissner@linux.ibm.com>
gcc/
PR target/100809
* config/rs6000/rs6000.md (udivti3): New insn.
(divti3): New insn.
(umodti3): New insn.
(modti3): New insn.
gcc/testsuite/
PR target/100809
* gcc.target/powerpc/p10-vdiv-vmod.c: New test.
Diff:
---
gcc/config/rs6000/rs6000.md | 34 ++++++++++++++++++++++++
gcc/testsuite/gcc.target/powerpc/p10-vdiv-vmod.c | 0
2 files changed, 34 insertions(+)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index dd9497929cd..9a1685bc1a8 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -3234,6 +3234,14 @@
[(set_attr "type" "div")
(set_attr "size" "<bits>")])
+(define_insn "udivti3"
+ [(set (match_operand:TI 0 "altivec_register_operand" "=v")
+ (udiv:TI (match_operand:TI 1 "altivec_register_operand" "v")
+ (match_operand:TI 2 "altivec_register_operand" "v")))]
+ "TARGET_POWER10 && TARGET_POWERPC64"
+ "vdivuq %0,%1,%2"
+ [(set_attr "type" "vecdiv")
+ (set_attr "size" "128")])
;; For powers of two we can do sra[wd]i/addze for divide and then adjust for
;; modulus. If it isn't a power of two, force operands into register and do
@@ -3324,6 +3332,15 @@
(set_attr "length" "8,12")
(set_attr "cell_micro" "not")])
+(define_insn "divti3"
+ [(set (match_operand:TI 0 "altivec_register_operand" "=v")
+ (div:TI (match_operand:TI 1 "altivec_register_operand" "v")
+ (match_operand:TI 2 "altivec_register_operand" "v")))]
+ "TARGET_POWER10 && TARGET_POWERPC64"
+ "vdivsq %0,%1,%2"
+ [(set_attr "type" "vecdiv")
+ (set_attr "size" "128")])
+
(define_expand "mod<mode>3"
[(set (match_operand:GPR 0 "gpc_reg_operand")
(mod:GPR (match_operand:GPR 1 "gpc_reg_operand")
@@ -3424,6 +3441,23 @@
(minus:GPR (match_dup 1)
(match_dup 3)))])
+(define_insn "umodti3"
+ [(set (match_operand:TI 0 "altivec_register_operand" "=v")
+ (umod:TI (match_operand:TI 1 "altivec_register_operand" "v")
+ (match_operand:TI 2 "altivec_register_operand" "v")))]
+ "TARGET_POWER10 && TARGET_POWERPC64"
+ "vmoduq %0,%1,%2"
+ [(set_attr "type" "vecdiv")
+ (set_attr "size" "128")])
+
+(define_insn "modti3"
+ [(set (match_operand:TI 0 "altivec_register_operand" "=v")
+ (mod:TI (match_operand:TI 1 "altivec_register_operand" "v")
+ (match_operand:TI 2 "altivec_register_operand" "v")))]
+ "TARGET_POWER10 && TARGET_POWERPC64"
+ "vmodsq %0,%1,%2"
+ [(set_attr "type" "vecdiv")
+ (set_attr "size" "128")])
\f
;; Logical instructions
;; The logical instructions are mostly combined by using match_operator,
diff --git a/gcc/testsuite/gcc.target/powerpc/p10-vdiv-vmod.c b/gcc/testsuite/gcc.target/powerpc/p10-vdiv-vmod.c
new file mode 100644
index 00000000000..e69de29bb2d
^ permalink raw reply [flat|nested] 3+ messages in thread
* [gcc(refs/users/meissner/heads/work058)] Generate 128-bit divide/modulus.
@ 2021-07-04 12:58 Michael Meissner
0 siblings, 0 replies; 3+ messages in thread
From: Michael Meissner @ 2021-07-04 12:58 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:12ce6b65d4b15e02862acf181ea243eddb713358
commit 12ce6b65d4b15e02862acf181ea243eddb713358
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Sun Jul 4 08:57:57 2021 -0400
Generate 128-bit divide/modulus.
This patch adds support for the VDIVSQ, VDIVUQ, VMODSQ, and VMODUQ
instructions to do 128-bit arithmetic.
2021-07-04 Michael Meissner <meissner@linux.ibm.com>
gcc/
PR target/100809
* config/rs6000/rs6000.md (udivti3): New insn.
(divti3): New insn.
(umodti3): New insn.
(modti3): New insn.
gcc/testsuite/
PR target/100809
* gcc.target/powerpc/p10-vdiv-vmod.c: New test.
Diff:
---
gcc/config/rs6000/rs6000.md | 34 ++++++++++++++++++++++
gcc/testsuite/gcc.target/powerpc/p10-vdivq-vmodq.c | 27 +++++++++++++++++
2 files changed, 61 insertions(+)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index dd9497929cd..9a1685bc1a8 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -3234,6 +3234,14 @@
[(set_attr "type" "div")
(set_attr "size" "<bits>")])
+(define_insn "udivti3"
+ [(set (match_operand:TI 0 "altivec_register_operand" "=v")
+ (udiv:TI (match_operand:TI 1 "altivec_register_operand" "v")
+ (match_operand:TI 2 "altivec_register_operand" "v")))]
+ "TARGET_POWER10 && TARGET_POWERPC64"
+ "vdivuq %0,%1,%2"
+ [(set_attr "type" "vecdiv")
+ (set_attr "size" "128")])
;; For powers of two we can do sra[wd]i/addze for divide and then adjust for
;; modulus. If it isn't a power of two, force operands into register and do
@@ -3324,6 +3332,15 @@
(set_attr "length" "8,12")
(set_attr "cell_micro" "not")])
+(define_insn "divti3"
+ [(set (match_operand:TI 0 "altivec_register_operand" "=v")
+ (div:TI (match_operand:TI 1 "altivec_register_operand" "v")
+ (match_operand:TI 2 "altivec_register_operand" "v")))]
+ "TARGET_POWER10 && TARGET_POWERPC64"
+ "vdivsq %0,%1,%2"
+ [(set_attr "type" "vecdiv")
+ (set_attr "size" "128")])
+
(define_expand "mod<mode>3"
[(set (match_operand:GPR 0 "gpc_reg_operand")
(mod:GPR (match_operand:GPR 1 "gpc_reg_operand")
@@ -3424,6 +3441,23 @@
(minus:GPR (match_dup 1)
(match_dup 3)))])
+(define_insn "umodti3"
+ [(set (match_operand:TI 0 "altivec_register_operand" "=v")
+ (umod:TI (match_operand:TI 1 "altivec_register_operand" "v")
+ (match_operand:TI 2 "altivec_register_operand" "v")))]
+ "TARGET_POWER10 && TARGET_POWERPC64"
+ "vmoduq %0,%1,%2"
+ [(set_attr "type" "vecdiv")
+ (set_attr "size" "128")])
+
+(define_insn "modti3"
+ [(set (match_operand:TI 0 "altivec_register_operand" "=v")
+ (mod:TI (match_operand:TI 1 "altivec_register_operand" "v")
+ (match_operand:TI 2 "altivec_register_operand" "v")))]
+ "TARGET_POWER10 && TARGET_POWERPC64"
+ "vmodsq %0,%1,%2"
+ [(set_attr "type" "vecdiv")
+ (set_attr "size" "128")])
\f
;; Logical instructions
;; The logical instructions are mostly combined by using match_operator,
diff --git a/gcc/testsuite/gcc.target/powerpc/p10-vdivq-vmodq.c b/gcc/testsuite/gcc.target/powerpc/p10-vdivq-vmodq.c
new file mode 100644
index 00000000000..cd29b0a4b6b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/p10-vdivq-vmodq.c
@@ -0,0 +1,27 @@
+/* { dg-require-effective-target lp64 } */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
+
+unsigned __int128 u_div(unsigned __int128 a, unsigned __int128 b)
+{
+ return a/b;
+}
+
+unsigned __int128 u_mod(unsigned __int128 a, unsigned __int128 b)
+{
+ return a%b;
+}
+__int128 s_div(__int128 a, __int128 b)
+{
+ return a/b;
+}
+
+__int128 s_mod(__int128 a, __int128 b)
+{
+ return a%b;
+}
+
+/* { dg-final { scan-assembler {\mvdivsq\M} } } */
+/* { dg-final { scan-assembler {\mvdivuq\M} } } */
+/* { dg-final { scan-assembler {\mvmodsq\M} } } */
+/* { dg-final { scan-assembler {\mvmoduq\M} } } */
^ permalink raw reply [flat|nested] 3+ messages in thread
* [gcc(refs/users/meissner/heads/work058)] Generate 128-bit divide/modulus.
@ 2021-07-04 6:12 Michael Meissner
0 siblings, 0 replies; 3+ messages in thread
From: Michael Meissner @ 2021-07-04 6:12 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:f11b462b55c9ad678e3cf5c8ef853d49259a72d4
commit f11b462b55c9ad678e3cf5c8ef853d49259a72d4
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Sun Jul 4 02:12:36 2021 -0400
Generate 128-bit divide/modulus.
This patch adds support for the VDIVSQ, VDIVUQ, VMODSQ, and VMODUQ
instructions to do 128-bit arithmetic.
2021-07-04 Michael Meissner <meissner@linux.ibm.com>
gcc/
PR target/100809
* config/rs6000/rs6000.md (udivti3): New insn.
(divti3): New insn.
(umodti3): New insn.
(modti3): New insn.
gcc/testsuite/
PR target/100809
* gcc.target/powerpc/p10-vdiv-vmod.c: New test.
Diff:
---
gcc/config/rs6000/rs6000.md | 34 ++++++++++++++++++++++++
gcc/testsuite/gcc.target/powerpc/p10-vdiv-vmod.c | 0
2 files changed, 34 insertions(+)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index dd9497929cd..9a1685bc1a8 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -3234,6 +3234,14 @@
[(set_attr "type" "div")
(set_attr "size" "<bits>")])
+(define_insn "udivti3"
+ [(set (match_operand:TI 0 "altivec_register_operand" "=v")
+ (udiv:TI (match_operand:TI 1 "altivec_register_operand" "v")
+ (match_operand:TI 2 "altivec_register_operand" "v")))]
+ "TARGET_POWER10 && TARGET_POWERPC64"
+ "vdivuq %0,%1,%2"
+ [(set_attr "type" "vecdiv")
+ (set_attr "size" "128")])
;; For powers of two we can do sra[wd]i/addze for divide and then adjust for
;; modulus. If it isn't a power of two, force operands into register and do
@@ -3324,6 +3332,15 @@
(set_attr "length" "8,12")
(set_attr "cell_micro" "not")])
+(define_insn "divti3"
+ [(set (match_operand:TI 0 "altivec_register_operand" "=v")
+ (div:TI (match_operand:TI 1 "altivec_register_operand" "v")
+ (match_operand:TI 2 "altivec_register_operand" "v")))]
+ "TARGET_POWER10 && TARGET_POWERPC64"
+ "vdivsq %0,%1,%2"
+ [(set_attr "type" "vecdiv")
+ (set_attr "size" "128")])
+
(define_expand "mod<mode>3"
[(set (match_operand:GPR 0 "gpc_reg_operand")
(mod:GPR (match_operand:GPR 1 "gpc_reg_operand")
@@ -3424,6 +3441,23 @@
(minus:GPR (match_dup 1)
(match_dup 3)))])
+(define_insn "umodti3"
+ [(set (match_operand:TI 0 "altivec_register_operand" "=v")
+ (umod:TI (match_operand:TI 1 "altivec_register_operand" "v")
+ (match_operand:TI 2 "altivec_register_operand" "v")))]
+ "TARGET_POWER10 && TARGET_POWERPC64"
+ "vmoduq %0,%1,%2"
+ [(set_attr "type" "vecdiv")
+ (set_attr "size" "128")])
+
+(define_insn "modti3"
+ [(set (match_operand:TI 0 "altivec_register_operand" "=v")
+ (mod:TI (match_operand:TI 1 "altivec_register_operand" "v")
+ (match_operand:TI 2 "altivec_register_operand" "v")))]
+ "TARGET_POWER10 && TARGET_POWERPC64"
+ "vmodsq %0,%1,%2"
+ [(set_attr "type" "vecdiv")
+ (set_attr "size" "128")])
\f
;; Logical instructions
;; The logical instructions are mostly combined by using match_operator,
diff --git a/gcc/testsuite/gcc.target/powerpc/p10-vdiv-vmod.c b/gcc/testsuite/gcc.target/powerpc/p10-vdiv-vmod.c
new file mode 100644
index 00000000000..e69de29bb2d
^ permalink raw reply [flat|nested] 3+ messages in thread
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