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* [gcc(refs/users/meissner/heads/work058)] Revert patches.
@ 2021-07-04 13:14 Michael Meissner
0 siblings, 0 replies; only message in thread
From: Michael Meissner @ 2021-07-04 13:14 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:363a169ca5f72930904ee82a31e8721c2104aa21
commit 363a169ca5f72930904ee82a31e8721c2104aa21
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Sun Jul 4 09:11:39 2021 -0400
Revert patches.
2021-07-04 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patch.
* config/rs6000/constraint.md (eQ): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): If the constant
can be loaded with LXVKQ, it is easy.
(lxvkq_operand): New predicate.
* config/rs6000/rs6000-protos.h (lxvkq_constant_p): New
declaration.
* config/rs6000/rs6000-cpus.h (ISA_3_1_MASKS_SERVER): Add -mlxvkq.
(POWERPC_MASKS): Add -mlxvkq.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
support for -mlxvkq.
(lxvkq_constant_p): New function.
(output_vec_const_move): Add support for generating lxvkq.
(rs6000_output_move_128bit): Add support for generating lxvkq.
(rs6000_opt_masks): Add -mlxvkq.
* config/rs6000/rs6000.opt (-mlxvkq): New option.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support to
generate lxvkq.
(vsx_mov<mode>_32bit): Add support to generate lxvkq.
gcc/testsuite/
Revert patch.
* gcc.target/powerpc/float128-constant.c: New test.
gcc/
Revert patch.
* config/rs6000/constraint.md (eD): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): If the constant
can be loaded with XXSPLTI32DX, it is easy.
(xxsplti32dx_operand): New predicate.
(easy_vector_constant): If the constant can be loaded with
XXSPLTI32DX, it is easy.
* config/rs6000/rs6000-protos.h (xxsplti32dx_constant_p): New
declaration.
* config/rs6000/rs6000-cpus.h (ISA_3_1_MASKS_SERVER): Add
-mxxsplti32dx.
(POWERPC_MASKS): Add -mxxsplti32dx.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
support for -mxxsplti32dx.
(xxsplti32dx_constant_float_p): New helper function.
(xxsplti32dx_constant_p): New function.
(output_vec_const_move): If the operand can be loaded with
XXSPLTI32DX, split it.
(rs6000_opt_masks): Add -mxxsplti32dx.
* config/rs6000/rs6000.md (movsf_hardfloat): Add support for
constants loaded with XXSPLTI32DX.
(mov<mode>_hardfloat32, FMOVE64 iterator): Add support for
constants loaded with XXSPLTI32DX.
(mov<mode>_hardfloat64, FMOVE64 iterator): Add support for
constants loaded with XXSPLTI32DX.
* config/rs6000/rs6000.opt (-mxxsplti32dx): New option.
* config/rs6000/vsx.md (UNSPEC_XXSPLTI32DX_CONST): New unspec.
(XXSPLTI32DX): New mode iterator.
(xxsplti32dx_<mode>): New insn and splitter for XXSPLTI32DX.
(xxsplti32dx_<mode>_first): New insn.
(xxsplti32dx_<mode>_second): New insn.
gcc/testsuite/
Revert patch.
* gcc.target/powerpc/vec-splat-constant-sf.c: Update insn count.
* gcc.target/powerpc/vec-splat-constant-df.c: Update insn count.
* gcc.target/powerpc/vec-splat-constant-v2df.c: Update insn
count.
2021-07-04 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patch.
* config/rs6000/constraints.md (eF): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): If we can load
the scalar constant with XXSPLTIDP, the floating point constant is
easy.
(xxspltidp_operand): New predicate.
(easy_vector_constant): If we can generate XXSPLTIDP, mark the
vector constant as easy.
* config/rs6000/rs6000-cpus.def (OTHER_POWER10_MASKS): Add
-mxxspltidp support.
(POWERPC_MASKS): Add -mxxspltidp support.
* config/rs6000/rs6000-protos.h (xxspltidp_constant_p): New
declaration.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
-mxxspltidp support.
(const_vector_element_all_same): New function.
(xxspltidp_constant_p): New function.
(output_vec_const_move): Add support for XXSPLTIDP.
(rs6000_opt_masks): Add -mxxspltidp support.
(rs6000_emit_xxspltidp_v2df): Change function to implement the
XXSPLTIDP instruction.
* config/rs6000/rs6000.md (movsf_hardfloat): Add XXSPLTIDP
support.
(mov<mode>_hardfloat32, FMOVE64 iterator): Add XXSPLTIDP support.
(mov<mode>_hardfloat64, FMOVE64 iterator): Add XXSPLTIDP support.
* config/rs6000/rs6000.opt (-mxxspltidp): New switch.
* config/rs6000/vsx.md (UNSPEC_XXSPLTIDP): Rename UNSPEC_XXSPLTID
to UNSPEC_XXSPLTIDP to match the instruction.
(xxspltidp_v2df): Use 'use' for the expand arguments, instead of
writing out an insn.
(xxspltidp_v2df_inst): Delete.
(XXSPLTIDP): New mode iterator.
(xxspltidp_<mode>_internal1): New define_insn_and_split.
(xxspltidp_<mode>_internal2): New define_insn.
gcc/testsuite/
Revert patch.
* gcc.target/powerpc/vec-splat-constant-sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-df.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2df.c: New test.
2021-07-04 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patch.
* config/rs6000/predicates.md (xxspltiw_operand): New predicate.
(easy_vector_constant): If we can use XXSPLTIW, the vector
constant is easy.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
-mxxspltiw support.
(xxspltib_constant_p): If we can generate XXSPLTIW, don't generate
a XXSPLTIB and an extend instruction.
(output_vec_const_move): Add support for loading up vector
constants with XXSPLTIW.
(rs6000_opt_masks): Add -mxxspltiw.
* config/rs6000/rs6000.h (SIGN_EXTEND_8BIT): New macro.
(SIGN_EXTEND_16BIT): New macro.
(SIGN_EXTEND_32BIT): New macro.
* config/rs6000/rs6000.opt (-mxxspltiw): New debug switch.
* config/rs6000/vsx.md (UNSPEC_XXSPLTIW): Delete.
(xxspltiw_v8hi): New insn.
(xxspltiw_v4si): Rewrite to generate a vector constant.
(xxspltiw_v4sf): Rewrite to generate a vector constant.
(xxspltiw_v4si_inst): Delete.
(xxspltiw_v4sf_inst): Delete.
(xxspltiw_v8hi_dup): New insn.
(xxspltiw_v4si_dup): New insn.
(xxspltiw_v4sf_dup): New insn.
(XXSPLTIW): New mode iterator.
(XXSPLTIW splitter): New insn splitter for XXSPLTIW.
gcc/testsuite/
Revert patch.
* gcc.target/powerpc/pr86731-fwrapv.c: Update insn counts on
power10.
* gcc.target/powerpc/vec-splati-runnable.c: Update insn counts.
* gcc.target/powerpc/vec-splat-constant-v4sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4si.c: New test.
* gcc.target/powerpc/vec-splat-constant-v8hi.c: New test.
2021-06-30 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patch.
PR target/101019
* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
-mprefixed-large-consts support.
(num_insns_constant_gpr): Add -mprefixed-large-consts support.
(rs6000_emit_set_long_const): Add -mprefixed-large-consts
support.
* config/rs6000/rs6000.opt (-mprefixed-large-consts): New switch.
gcc/testsuite/
Revert patch.
PR target/101019
* gcc.target/powerpc/prefix-large-const.c: New test.
Diff:
---
gcc/config/rs6000/constraints.md | 16 -
gcc/config/rs6000/predicates.md | 82 -----
gcc/config/rs6000/rs6000-protos.h | 4 -
gcc/config/rs6000/rs6000.c | 406 +--------------------
gcc/config/rs6000/rs6000.h | 19 -
gcc/config/rs6000/rs6000.md | 81 +---
gcc/config/rs6000/rs6000.opt | 20 -
gcc/config/rs6000/vsx.md | 298 +++------------
.../gcc.target/powerpc/float128-constant.c | 144 --------
gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv.c | 9 +-
.../gcc.target/powerpc/prefix-large-const.c | 57 ---
.../gcc.target/powerpc/vec-splat-constant-df.c | 63 ----
.../gcc.target/powerpc/vec-splat-constant-sf.c | 63 ----
.../gcc.target/powerpc/vec-splat-constant-v2df.c | 66 ----
.../gcc.target/powerpc/vec-splat-constant-v4sf.c | 66 ----
.../gcc.target/powerpc/vec-splat-constant-v4si.c | 51 ---
.../gcc.target/powerpc/vec-splat-constant-v8hi.c | 53 ---
.../gcc.target/powerpc/vec-splati-runnable.c | 4 +-
18 files changed, 89 insertions(+), 1413 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index d14ce98e9ac..561ce9797af 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -208,27 +208,11 @@
(and (match_code "const_int")
(match_test "((- (unsigned HOST_WIDE_INT) ival) + 0x8000) < 0x10000")))
-;; SF/DF/V2DF/DI/V2DI scalar or vector constant that can be loaded with a pair
-;; of XXSPLTI32DX instructions.
-(define_constraint "eD"
- "A vector constant that can be loaded with XXSPLTI32DX instructions."
- (match_operand 0 "xxsplti32dx_operand"))
-
-;; SF/DF/V2DF scalar or vector constant that can be loaded with XXSPLTIDP
-(define_constraint "eF"
- "A vector constant that can be loaded with the XXSPLTIDP instruction."
- (match_operand 0 "xxspltidp_operand"))
-
;; 34-bit signed integer constant
(define_constraint "eI"
"A signed 34-bit integer constant if prefixed instructions are supported."
(match_operand 0 "cint34_operand"))
-;; KF/TF scalar than can be loaded with XVKQ
-(define_constraint "eQ"
- "An IEEE 128-bit constant that can be loaded with the LXVKQ instruction."
- (match_operand 0 "lxvkq_operand"))
-
;; Floating-point constraints. These two are defined so that insn
;; length attributes can be calculated exactly.
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 9584663ce16..121cbf14810 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -601,21 +601,6 @@
if (TARGET_VSX && op == CONST0_RTX (mode))
return 1;
- /* If we have the ISA 3.1 XXSPLTIDP instruction, see if the constant can
- be loaded with that instruction. */
- if (xxspltidp_operand (op, mode))
- return 1;
-
- /* If we have the ISA 3.1 XXSPLTI32DX instruction, see if the constant can
- be loaded with a pair of those instructions. */
- if (xxsplti32dx_operand (op, mode))
- return 1;
-
- /* If we have the ISA 3.1 LXVKQ instruction, see if the constant can be loaded
- with that instruction. */
- if (lxvkq_operand (op, mode))
- return 1;
-
/* Otherwise consider floating point constants hard, so that the
constant gets pushed to memory during the early RTL phases. This
has the advantage that double precision constants that can be
@@ -655,64 +640,6 @@
return num_insns == 1;
})
-;; Return 1 if the operand is a CONST_VECTOR that can be loaded with the
-;; XXSPLTIW instruction. Do not return 1 if the constant can be generated with
-;; XXSPLTIB or VSPLTIS{H,W}
-(define_predicate "xxspltiw_operand"
- (match_code "const_vector")
-{
- if (!TARGET_XXSPLTIW)
- return false;
-
- if (mode != V8HImode && mode != V4SImode && mode != V4SFmode)
- return false;
-
- rtx element = CONST_VECTOR_ELT (op, 0);
- for (size_t i = 1; i < GET_MODE_NUNITS (mode); i++)
- if (!rtx_equal_p (element, CONST_VECTOR_ELT (op, i)))
- return false;
-
- if (element == CONST0_RTX (GET_MODE_INNER (mode)))
- return false;
-
- if (CONST_INT_P (element) && EASY_VECTOR_15 (INTVAL (element)))
- return false;
-
- return true;
-})
-
-;; Return 1 if operand is a SF/DF CONST_DOUBLE or V2DF CONST_VECTOR that can be
-;; loaded via the ISA 3.1 XXSPLTIDP instruction. Do not return true if the
-;; value is 0.0, since that is easy to generate without using XXSPLTIDP.
-(define_predicate "xxspltidp_operand"
- (match_code "const_double,const_vector,vec_duplicate")
-{
- if (op == CONST0_RTX (mode))
- return false;
-
- HOST_WIDE_INT value = 0;
- return xxspltidp_constant_p (op, mode, &value);
-})
-
-;; Return 1 if operand is a SF/DF CONST_DOUBLE or V2DF CONST_VECTOR that can be
-;; loaded via a pair f ISA 3.1 XXSPLTI32DX instructions. Do not return true if
-;; the value can be loaded with the XXSPLTIDP instruction or XXSPLTIB to load 0.
-(define_predicate "xxsplti32dx_operand"
- (match_code "const_double,const_vector,vec_duplicate")
-{
- HOST_WIDE_INT high = 0, low = 0;
- return xxsplti32dx_constant_p (op, mode, &high, &low);
-})
-
-;; Return 1 if the operand is an IEEE 128-bit special constant that can be
-;; loaded with the LXVKQ instruction.
-(define_predicate "lxvkq_operand"
- (match_code "const_double")
-{
- int immediate = 0;
- return lxvkq_constant_p (op, mode, &immediate);
-})
-
;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
;; vector register without using memory.
(define_predicate "easy_vector_constant"
@@ -726,15 +653,6 @@
if (zero_constant (op, mode) || all_ones_constant (op, mode))
return true;
- if (xxspltiw_operand (op, mode))
- return true;
-
- if (xxspltidp_operand (op, mode))
- return true;
-
- if (xxsplti32dx_operand (op, mode))
- return true;
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (op, mode, &num_insns, &value))
return true;
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 600d64424f5..94bf961c6b7 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -32,10 +32,6 @@ extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, int, int, int,
extern bool easy_altivec_constant (rtx, machine_mode);
extern bool xxspltib_constant_p (rtx, machine_mode, int *, int *);
-extern bool xxspltidp_constant_p (rtx, machine_mode, HOST_WIDE_INT *);
-extern bool xxsplti32dx_constant_p (rtx, machine_mode, HOST_WIDE_INT *,
- HOST_WIDE_INT *);
-extern bool lxvkq_constant_p (rtx, machine_mode, int *);
extern int vspltis_shifted (rtx);
extern HOST_WIDE_INT const_vector_elt_as_int (rtx, unsigned int);
extern bool macho_lo_sum_memory_operand (rtx, machine_mode);
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 7dd7dd8bc1e..dd24e11ad8d 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -4502,36 +4502,6 @@ rs6000_option_override_internal (bool global_init_p)
if (!TARGET_PCREL && TARGET_PCREL_OPT)
rs6000_isa_flags &= ~OPTION_MASK_PCREL_OPT;
- if (TARGET_PREFIXED_LARGE_CONSTS < 0)
- TARGET_PREFIXED_LARGE_CONSTS = TARGET_PREFIXED;
- else if (TARGET_PREFIXED_LARGE_CONSTS > 0 && !TARGET_PREFIXED)
- error ("%qs requires %qs", "-mprefixed-large-consts", "-mprefixed");
-
- if (TARGET_XXSPLTI32DX < 0)
- TARGET_XXSPLTI32DX = TARGET_PREFIXED;
- else if (TARGET_XXSPLTI32DX > 0 && !TARGET_PREFIXED)
- error ("%qs requires %qs", "-mxxspli32dx", "-mprefixed");
-
- if (TARGET_XXSPLTIDP < 0)
- TARGET_XXSPLTIDP = TARGET_PREFIXED;
- else if (TARGET_XXSPLTIDP > 0 && !TARGET_PREFIXED)
- error ("%qs requires %qs", "-mxxsplidp", "-mprefixed");
-
- if (TARGET_XXSPLTIW < 0)
- TARGET_XXSPLTIW = TARGET_PREFIXED;
- else if (TARGET_XXSPLTIW > 0 && !TARGET_PREFIXED)
- error ("%qs requires %qs", "-mxxspliw", "-mprefixed");
-
- if (TARGET_LXVKQ < 0)
- TARGET_LXVKQ = (TARGET_POWER10 && TARGET_FLOAT128_HW);
- else if (TARGET_LXVKQ > 0)
- {
- if (!TARGET_POWER10)
- error ("%qs requires %qs", "-mlxvkq", "-mcpu=power10");
- else if (!TARGET_FLOAT128_HW)
- error ("%qs requires %qs", "-mlxvkq", "-mfloat128-hardware");
- }
-
/* Possibly set the const_anchor to the maximum value, based on whether we
have prefixed addressing. */
if (TARGET_CONST_ANCHOR)
@@ -5975,20 +5945,9 @@ num_insns_constant_gpr (HOST_WIDE_INT value)
&& (value >> 31 == -1 || value >> 31 == 0))
return 1;
- /* PADDI can support up to 34 bit signed integers, or using a combination of
- PADDI and shift left. */
- else if (TARGET_PREFIXED_LARGE_CONSTS)
- {
- if (SIGNED_INTEGER_34BIT_P (value))
- return 1;
-
- /* PLI and SLDI. */
- if ((value & 0xffffffff) == 0)
- return 2;
-
- /* PLI, SLDI, PADDI. */
- return 3;
- }
+ /* PADDI can support up to 34 bit signed integers. */
+ else if (TARGET_PREFIXED && SIGNED_INTEGER_34BIT_P (value))
+ return 1;
else if (TARGET_POWERPC64)
{
@@ -6529,11 +6488,9 @@ xxspltib_constant_p (rtx op,
/* See if we could generate vspltisw/vspltish directly instead of xxspltib +
sign extend. Special case 0/-1 to allow getting any VSX register instead
- of an Altivec register. Also if we can generate a XXSPLTIW instruction,
- don't emit a XXSPLTIB and an extend instruction. */
- if ((mode == V4SImode || mode == V8HImode)
- && !IN_RANGE (value, -1, 0)
- && (EASY_VECTOR_15 (value) || TARGET_XXSPLTIW))
+ of an Altivec register. */
+ if ((mode == V4SImode || mode == V8HImode) && !IN_RANGE (value, -1, 0)
+ && EASY_VECTOR_15 (value))
return false;
/* Return # of instructions and the constant byte for XXSPLTIB. */
@@ -6550,289 +6507,6 @@ xxspltib_constant_p (rtx op,
return true;
}
-/* Return the element of a constant vector whose elements are all the same. In
- addition if VEC_DUPLICATE is used, return the element being duplicated. If
- neither is true, return NULL_RTX. */
-
-static rtx
-const_vector_element_all_same (rtx op)
-{
- if (GET_CODE (op) == VEC_DUPLICATE)
- {
- rtx element = XEXP (op, 0);
- return (CONST_INT_P (element) || CONST_DOUBLE_P (element)
- ? element
- : NULL_RTX);
- }
-
- else if (GET_CODE (op) == CONST_VECTOR)
- {
- machine_mode mode = GET_MODE (op);
- size_t n_elts = GET_MODE_NUNITS (mode);
- rtx element = CONST_VECTOR_ELT (op, 0);
-
- for (size_t i = 1; i < n_elts; i++)
- if (!rtx_equal_p (element, CONST_VECTOR_ELT (op, 1)))
- return NULL_RTX;
-
- return element;
- }
-
- return NULL_RTX;
-}
-
-/* Return true if OP is of the given MODE and can be synthesized with ISA 3.1
- XXSPLTIDP instruction.
-
- Return the constant that is being split via CONSTANT_PTR to use in the
- XXSPLTIDP instruction. */
-
-bool
-xxspltidp_constant_p (rtx op,
- machine_mode mode,
- HOST_WIDE_INT *constant_ptr)
-{
- *constant_ptr = 0;
-
- if (!TARGET_XXSPLTIDP)
- return false;
-
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- rtx element = op;
- if (mode == V2DFmode)
- {
- element = const_vector_element_all_same (op);
- if (!element)
- return false;
-
- mode = DFmode;
- }
-
- if (mode != SFmode && mode != DFmode)
- return false;
-
- if (GET_MODE (element) != mode)
- return false;
-
- if (!CONST_DOUBLE_P (element))
- return false;
-
- /* Don't return true for 0.0 since that is easy to create without
- XXSPLTIDP. */
- if (element == CONST0_RTX (mode))
- return false;
-
- /* If the value doesn't fit in a SFmode, exactly, we can't use XXSPLTIDP. */
- const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (element);
- if (!exact_real_truncate (SFmode, rv))
- return 0;
-
- long value;
- REAL_VALUE_TO_TARGET_SINGLE (*rv, value);
-
- /* Test for SFmode denormal (exponent is 0, mantissa field is non-zero). */
- if (((value & 0x7F800000) == 0) && ((value & 0x7FFFFF) != 0))
- return false;
-
- *constant_ptr = value;
- return true;
-}
-
-/* Return true if OP is a floating point constant that can be loaded with the
- XXSPLTI32DX instruction. If the constant can be loaded with the simpler
- XXSPLTIDP (constants that can fit as SFmode constants) or XXSPLTIB (0.0)
- instructions, return false.
-
- Return the two 32-bit constants to use in the two XXSPLTI32DX instructions
- via HIGH_PTR and LOW_PTR. */
-
-static bool
-xxsplti32dx_constant_float_p (rtx op,
- machine_mode mode,
- HOST_WIDE_INT *high_ptr,
- HOST_WIDE_INT *low_ptr)
-{
- HOST_WIDE_INT xxspltidp_value = 0;
-
- if (!CONST_DOUBLE_P (op))
- return false;
-
- if (mode != SFmode && mode != DFmode)
- return false;
-
- if (op == CONST0_RTX (mode))
- return false;
-
- if (xxspltidp_constant_p (op, mode, &xxspltidp_value))
- return false;
-
- long high_low[2];
- const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (op);
- REAL_VALUE_TO_TARGET_DOUBLE (*rv, high_low);
-
- /* The double precision value is laid out in memory order. We need to undo
- this for XXSPLTI32DX. */
- if (!BYTES_BIG_ENDIAN)
- std::swap (high_low[0], high_low[1]);
-
- *high_ptr = high_low[0];
- *low_ptr = high_low[1];
- return true;
-}
-
-/* Return true if OP is of the given MODE and can be synthesized with ISA 3.1
- XXSPLTI32DX instruction. If the instruction can be synthesized with
- XXSPLTIDP or is 0/-1, return false.
-
- We handle the following types of constants:
-
- 1) vector double constants where each element is the same and you can't
- load the constant with XXSPLTIDP;
-
- 2) vector long long constants where each element is the same;
-
- 3) Scalar floating point constants that can't be loaded with XXSPLTIDP.
-
- Return the two 32-bit constants to use in the two XXSPLTI32DX instructions
- via HIGH_PTR and LOW_PTR. */
-
-bool
-xxsplti32dx_constant_p (rtx op,
- machine_mode mode,
- HOST_WIDE_INT *high_ptr,
- HOST_WIDE_INT *low_ptr)
-{
- *high_ptr = *low_ptr = 0;
-
- if (!TARGET_XXSPLTI32DX)
- return false;
-
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- if (op == CONST0_RTX (mode))
- return false;
-
- switch (mode)
- {
- default:
- break;
-
- case E_V2DFmode:
- {
- rtx ele = const_vector_element_all_same (op);
- if (!ele)
- return false;
-
- return xxsplti32dx_constant_float_p (ele, DFmode, high_ptr, low_ptr);
- }
-
- case E_SFmode:
- case E_DFmode:
- return xxsplti32dx_constant_float_p (op, mode, high_ptr, low_ptr);
-
- case E_V2DImode:
- {
- rtx ele = const_vector_element_all_same (op);
- if (!ele)
- return false;
-
- /* If we can generate XXSPLTIB and VEXTSB2D, don't return true. */
- HOST_WIDE_INT value = INTVAL (ele);
- if (IN_RANGE (value, -128, 127))
- return false;
-
- *high_ptr = value >> 32;
- *low_ptr = value & 0xffffffff;
- return true;
- }
- }
-
- return false;
-}
-
-/* Return true if OP is of the given MODE is one of the 18 special values that
- can be generated with the LXVKQ instruction.
-
- Return the constant that will go in the LXVKQ instruction.
-
- The LXVKQ immediates are:
- 1 - 7: 1.0 .. 7.0.
- 8: Positive infinity.
- 9: Default quiet NaN.
- 16: -0.0.
- 17 - 23: -1.0 .. 7.0.
- 24: Negative infinity. */
-
-bool
-lxvkq_constant_p (rtx op,
- machine_mode mode,
- int *imm_p)
-{
- *imm_p = -1;
-
- if (!TARGET_LXVKQ)
- return false;
-
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- if (!FLOAT128_IEEE_P (mode))
- return false;
-
- if (!CONST_DOUBLE_P (op))
- return false;
-
- /* All of the values generated can be expressed as SFmode values, so if it
- doesn't fit in SFmode, exit. */
- const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (op);
- if (!exact_real_truncate (SFmode, rv))
- return 0;
-
- /* +/- Inifinity is 8/24. */
- if (REAL_VALUE_ISINF (*rv))
- {
- *imm_p = real_isneg (rv) ? 24 : 8;
- return true;
- }
-
- /* NaN is 9. */
- if (REAL_VALUE_ISNAN (*rv) && !REAL_VALUE_NEGATIVE (*rv))
- {
- *imm_p = 9;
- return true;
- }
-
- /* -0.0 is 16. */
- if (REAL_VALUE_MINUS_ZERO (*rv))
- {
- *imm_p = 16;
- return true;
- }
-
- /* The other values are all integers 1..7, and -1..-7. */
- if (!real_isinteger (rv, mode))
- return false;
-
- HOST_WIDE_INT value = real_to_integer (rv);
- if (value >= 1 && value <= 7)
- {
- *imm_p = value;
- return true;
- }
- else if (value >= -7 && value <= -1)
- {
- /* Subtraction is used because value is negative. */
- *imm_p = 16 - value;
- return true;
- }
-
- /* We can't load the value with LXVKQ. */
- return false;
-}
-
const char *
output_vec_const_move (rtx *operands)
{
@@ -6849,7 +6523,6 @@ output_vec_const_move (rtx *operands)
bool dest_vmx_p = ALTIVEC_REGNO_P (REGNO (dest));
int xxspltib_value = 256;
int num_insns = -1;
- int lxvkq_immediate = 0;
if (zero_constant (vec, mode))
{
@@ -6878,19 +6551,6 @@ output_vec_const_move (rtx *operands)
gcc_unreachable ();
}
- if (xxspltiw_operand (vec, mode)
- || xxspltidp_operand (vec, mode))
- return "#";
-
- if (xxsplti32dx_operand (vec, mode))
- return "#";
-
- if (lxvkq_constant_p (vec, mode, &lxvkq_immediate))
- {
- operands[2] = GEN_INT (lxvkq_immediate);
- return "lxvkq %x0,%2";
- }
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
{
@@ -10453,48 +10113,7 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c)
rtx two = gen_rtx_ASHIFT (DImode, temp, GEN_INT (32));
emit_move_insn (dest, gen_rtx_IOR (DImode, one, two));
}
- else if (TARGET_PREFIXED_LARGE_CONSTS)
- {
- HOST_WIDE_INT low_32bit = ud1 | (ud2 << 16);
- HOST_WIDE_INT high_32bit = ud3 | (ud4 << 16);
-
- temp = !can_create_pseudo_p () ? copy_rtx (dest) : gen_reg_rtx (DImode);
- emit_move_insn (temp, GEN_INT (high_32bit));
-
- if (!low_32bit)
- emit_insn (gen_ashldi3 (dest, temp, GEN_INT (32)));
- else
- {
- rtx temp2 = (!can_create_pseudo_p ()
- ? copy_rtx (dest)
- : gen_reg_rtx (DImode));
-
- emit_insn (gen_ashldi3 (temp2, temp, GEN_INT (32)));
-
- /* See if a simple ORI or ORIS will suffice to fill in the
- constant. */
- if (ud2 == 0)
- emit_insn (gen_iordi3 (dest, temp2, GEN_INT (ud1)));
- else if (ud1 == 0)
- emit_insn (gen_iordi3 (dest, temp2, GEN_INT (ud2 << 16)));
- /* If the register is not r0, we can do a PADDI. However, if the
- register is r0, we need to do an ORI and ORIS instead of a PADDI.
- This is because R0 as the register is interpreted as 0 and not
- R0. */
- else if (REGNO (dest) != FIRST_GPR_REGNO)
- emit_insn (gen_adddi3 (dest, temp2, GEN_INT (low_32bit)));
- else
- {
- rtx temp3 = (!can_create_pseudo_p ()
- ? copy_rtx (dest)
- : gen_reg_rtx (DImode));
-
- emit_insn (gen_iordi3 (temp3, temp2, GEN_INT (ud2 << 16)));
- emit_insn (gen_iordi3 (dest, temp3, GEN_INT (ud1)));
- }
- }
- }
- else if ((ud4 == 0xaffff && (ud3 & 0x8000))
+ else if ((ud4 == 0xffff && (ud3 & 0x8000))
|| (ud4 == 0 && ! (ud3 & 0x8000)))
{
temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
@@ -13627,7 +13246,6 @@ rs6000_output_move_128bit (rtx operands[])
int src_regno;
bool dest_gpr_p, dest_fp_p, dest_vmx_p, dest_vsx_p;
bool src_gpr_p, src_fp_p, src_vmx_p, src_vsx_p;
- int lxvkq_immediate = 0;
if (REG_P (dest))
{
@@ -13772,14 +13390,6 @@ rs6000_output_move_128bit (rtx operands[])
}
/* Constants. */
- else if (dest_vmx_p
- && CONST_DOUBLE_P (src)
- && lxvkq_constant_p (src, mode, &lxvkq_immediate))
- {
- operands[2] = GEN_INT (lxvkq_immediate);
- return "lxvkq %x0,%2";
- }
-
else if (dest_regno >= 0
&& (CONST_INT_P (src)
|| CONST_WIDE_INT_P (src)
@@ -28351,7 +27961,7 @@ rs6000_emit_xxspltidp_v2df (rtx dst, long value)
inform (input_location,
"the result for the xxspltidp instruction "
"is undefined for subnormal input values");
- emit_insn (gen_xxspltidp_v2df_internal2 (dst, GEN_INT (value)));
+ emit_insn( gen_xxspltidp_v2df_inst (dst, GEN_INT (value)));
}
/* Implement TARGET_ASM_GENERATE_PIC_ADDR_DIFF_VEC. */
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 75daa4c82d3..c5f38f26649 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -2613,22 +2613,3 @@ while (0)
rs6000_asm_output_opcode (STREAM); \
} \
while (0)
-
-/* Provide macros for sign-extending values. */
-#if HOST_BITS_PER_CHAR == 8
-#define SIGN_EXTEND_8BIT(X) ((HOST_WIDE_INT)(signed char)(X))
-#else
-#define SIGN_EXTEND_8BIT(X) ((((X) & 0xff) ^ 0x80) - 0x80)
-#endif
-
-#if HOST_BITS_PER_SHORT == 16
-#define SIGN_EXTEND_16BIT(X) ((HOST_WIDE_INT)(short)(X))
-#else
-#define SIGN_EXTEND_16BIT(X) ((((X) & 0xffff) ^ 0x8000) - 0x8000)
-#endif
-
-#if HOST_BITS_PER_INT == 32
-#define SIGN_EXTEND_32BIT(X) ((HOST_WIDE_INT)(int)(X))
-#else
-#define SIGN_EXTEND_32BIT(X) ((((X) & 0xffffffff) ^ 0x80000000) - 0x80000000)
-#endif
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 9a1685bc1a8..4e53cf28dde 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -7723,17 +7723,17 @@
;;
;; LWZ LFS LXSSP LXSSPX STFS STXSSP
;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP
-;; MR MT<x> MF<x> NOP XXSPLTIDP XXSPLTI32DX
+;; MR MT<x> MF<x> NOP
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, wY,
Z, m, wa, !r, f, wa,
- !r, *c*l, !r, *h, wa, wa")
+ !r, *c*l, !r, *h")
(match_operand:SF 1 "input_operand"
"m, m, wY, Z, f, v,
wa, r, j, j, f, wa,
- r, r, *h, 0, eF, eD"))]
+ r, r, *h, 0"))]
"(register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))
&& TARGET_HARD_FLOAT
@@ -7755,29 +7755,15 @@
mr %0,%1
mt%0 %1
mf%1 %0
- nop
- #
- #"
+ nop"
[(set_attr "type"
"load, fpload, fpload, fpload, fpstore, fpstore,
fpstore, store, veclogical, integer, fpsimple, fpsimple,
- *, mtjmpr, mfjmpr, *, vecperm, vecperm")
+ *, mtjmpr, mfjmpr, *")
(set_attr "isa"
"*, *, p9v, p8v, *, p9v,
p8v, *, *, *, *, *,
- *, *, *, *, p10, p10")
- (set_attr "prefixed"
- "*, *, *, *, *, *,
- *, *, *, *, *, *,
- *, *, *, *, yes, yes")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *, *,
- *, *, *, *, *, *,
- *, *, *, *, *, 2")
- (set_attr "num_insns"
- "*, *, *, *, *, *,
- *, *, *, *, *, *,
- *, *, *, *, *, 2")])
+ *, *, *, *")])
;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ
;; FMR MR MT%0 MF%1 NOP
@@ -8037,18 +8023,18 @@
;; STFD LFD FMR LXSD STXSD
;; LXSD STXSD XXLOR XXLXOR GPR<-0
-;; LWZ STW MR XXSPLTIDP XXSPLTI32DX
+;; LWZ STW MR
(define_insn "*mov<mode>_hardfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
- Y, r, !r, wa, wa")
+ Y, r, !r")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
- r, Y, r, eF, eD"))]
+ r, Y, r"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8065,34 +8051,20 @@
#
#
#
- #
- #
#"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, two,
- store, load, two, vecperm, vecperm")
+ store, load, two")
(set_attr "size" "64")
(set_attr "length"
"*, *, *, *, *,
*, *, *, *, 8,
- 8, 8, 8, *, *")
+ 8, 8, 8")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
- *, *, *, p10, p10")
- (set_attr "prefixed"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, yes, yes")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, 2")
- (set_attr "num_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, 2")])
+ *, *, *")])
;; STW LWZ MR G-const H-const F-const
@@ -8119,19 +8091,19 @@
;; STFD LFD FMR LXSD STXSD
;; LXSDX STXSDX XXLOR XXLXOR LI 0
;; STD LD MR MT{CTR,LR} MF{CTR,LR}
-;; NOP MFVSRD MTVSRD XXSPLTIDP XXSPLTI32DX
+;; NOP MFVSRD MTVSRD
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
YZ, r, !r, *c*l, !r,
- *h, r, <f64_dm>, wa, wa")
+ *h, r, <f64_dm>")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
r, YZ, r, r, *h,
- 0, <f64_dm>, r, eF, eD"))]
+ 0, <f64_dm>, r"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8153,35 +8125,18 @@
mf%1 %0
nop
mfvsrd %0,%x1
- mtvsrd %x0,%1
- #
- #"
+ mtvsrd %x0,%1"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, integer,
store, load, *, mtjmpr, mfjmpr,
- *, mfvsr, mtvsr, vecperm, vecperm")
+ *, mfvsr, mtvsr")
(set_attr "size" "64")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
*, *, *, *, *,
- *, p8v, p8v, p10, p10")
- (set_attr "prefixed"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- *, *, *, yes, yes")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, 2")
- (set_attr "num_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, *")])
+ *, p8v, p8v")])
;; STD LD MR MT<SPR> MF<SPR> G-const
;; H-const F-const Special
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 8ac78c369a4..70f89d42113 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -643,23 +643,3 @@ Generate code that will run in privileged state.
mconst-anchor
Target Undocumented Var(TARGET_CONST_ANCHOR) Save
Set targetm.const_anchor
-
-mprefixed-large-consts
-Target Undocumented Var(TARGET_PREFIXED_LARGE_CONSTS) Init(-1) Save
-Generate (do not generate) PLI/SLDI/PADDI to load large constants.
-
-mxxspltiw
-Target Undocumented Var(TARGET_XXSPLTIW) Init(-1) Save
-Generate (do not generate) XXSPLTIW instructions.
-
-mxxspltidp
-Target Undocumented Var(TARGET_XXSPLTIDP) Init(-1) Save
-Generate (do not generate) XXSPLTIDP instructions.
-
-mxxsplti32dx
-Target Undocumented Var(TARGET_XXSPLTI32DX) Init(-1) Save
-Generate (do not generate) XXSPLTI32DX instructions.
-
-mlxvkq
-Target Undocumented Var(TARGET_LXVKQ) Init(-1) Save
-Generate (do not generate) LXVKQ instructions.
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 5b47379b7f9..e912641abb8 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -389,9 +389,9 @@
UNSPEC_VDIVES
UNSPEC_VDIVEU
UNSPEC_XXEVAL
- UNSPEC_XXSPLTIDP
+ UNSPEC_XXSPLTIW
+ UNSPEC_XXSPLTID
UNSPEC_XXSPLTI32DX
- UNSPEC_XXSPLTI32DX_CONST
UNSPEC_XXBLEND
UNSPEC_XXPERMX
])
@@ -1192,17 +1192,17 @@
;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR)
;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW
-;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX) LXVKQ
+;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX)
(define_insn "vsx_mov<mode>_64bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, r, we, ?wQ,
?&r, ??r, ??Y, <??r>, wa, v,
- ?wa, v, <??r>, wZ, v, wa")
+ ?wa, v, <??r>, wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, we, r, r,
wQ, Y, r, r, wE, jwM,
- ?jwM, W, <nW>, v, wZ, eQ"))]
+ ?jwM, W, <nW>, v, wZ"))]
"TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
&& (register_operand (operands[0], <MODE>mode)
@@ -1213,37 +1213,37 @@
[(set_attr "type"
"vecstore, vecload, vecsimple, mtvsr, mfvsr, load,
store, load, store, *, vecsimple, vecsimple,
- vecsimple, *, *, vecstore, vecload, vecsimple")
+ vecsimple, *, *, vecstore, vecload")
(set_attr "num_insns"
"*, *, *, 2, *, 2,
2, 2, 2, 2, *, *,
- *, 5, 2, *, *, *")
+ *, 5, 2, *, *")
(set_attr "max_prefixed_insns"
"*, *, *, *, *, 2,
2, 2, 2, 2, *, *,
- *, *, *, *, *, *")
+ *, *, *, *, *")
(set_attr "length"
"*, *, *, 8, *, 8,
8, 8, 8, 8, *, *,
- *, 20, 8, *, *, *")
+ *, 20, 8, *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
*, *, *, *, p9v, *,
- <VSisa>, *, *, *, *, p10")])
+ <VSisa>, *, *, *, *")])
;; VSX store VSX load VSX move GPR load GPR store GPR move
;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const
-;; LVX (VMX) STVX (VMX) LXVKQ
+;; LVX (VMX) STVX (VMX)
(define_insn "*vsx_mov<mode>_32bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, ??r, ??Y, <??r>,
wa, v, ?wa, v, <??r>,
- wZ, v, wa")
+ wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, Y, r, r,
wE, jwM, ?jwM, W, <nW>,
- v, wZ, eQ"))]
+ v, wZ"))]
"!TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
&& (register_operand (operands[0], <MODE>mode)
@@ -1254,15 +1254,15 @@
[(set_attr "type"
"vecstore, vecload, vecsimple, load, store, *,
vecsimple, vecsimple, vecsimple, *, *,
- vecstore, vecload, vecsimple")
+ vecstore, vecload")
(set_attr "length"
"*, *, *, 16, 16, 16,
*, *, *, 20, 16,
- *, *, *")
+ *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
p9v, *, <VSisa>, *, *,
- *, *, p10")])
+ *, *")])
;; Explicit load/store expanders for the builtin functions
(define_expand "vsx_load_<mode>"
@@ -6406,10 +6406,41 @@
"vmulld %0,%1,%2"
[(set_attr "type" "veccomplex")])
+;; XXSPLTIW built-in function support
+(define_insn "xxspltiw_v4si"
+ [(set (match_operand:V4SI 0 "register_operand" "=wa")
+ (unspec:V4SI [(match_operand:SI 1 "s32bit_cint_operand" "n")]
+ UNSPEC_XXSPLTIW))]
+ "TARGET_POWER10"
+ "xxspltiw %x0,%1"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
+(define_expand "xxspltiw_v4sf"
+ [(set (match_operand:V4SF 0 "register_operand" "=wa")
+ (unspec:V4SF [(match_operand:SF 1 "const_double_operand" "n")]
+ UNSPEC_XXSPLTIW))]
+ "TARGET_POWER10"
+{
+ long long value = rs6000_const_f32_to_i32 (operands[1]);
+ emit_insn (gen_xxspltiw_v4sf_inst (operands[0], GEN_INT (value)));
+ DONE;
+})
+
+(define_insn "xxspltiw_v4sf_inst"
+ [(set (match_operand:V4SF 0 "register_operand" "=wa")
+ (unspec:V4SF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
+ UNSPEC_XXSPLTIW))]
+ "TARGET_POWER10"
+ "xxspltiw %x0,%1"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
;; XXSPLTIDP built-in function support
(define_expand "xxspltidp_v2df"
- [(use (match_operand:V2DF 0 "register_operand" ))
- (use (match_operand:SF 1 "const_double_operand"))]
+ [(set (match_operand:V2DF 0 "register_operand" )
+ (unspec:V2DF [(match_operand:SF 1 "const_double_operand")]
+ UNSPEC_XXSPLTID))]
"TARGET_POWER10"
{
long value = rs6000_const_f32_to_i32 (operands[1]);
@@ -6417,6 +6448,15 @@
DONE;
})
+(define_insn "xxspltidp_v2df_inst"
+ [(set (match_operand:V2DF 0 "register_operand" "=wa")
+ (unspec:V2DF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
+ UNSPEC_XXSPLTID))]
+ "TARGET_POWER10"
+ "xxspltidp %x0,%1"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
;; XXSPLTI32DX built-in function support
(define_expand "xxsplti32dx_v4si"
[(set (match_operand:V4SI 0 "register_operand" "=wa")
@@ -6547,225 +6587,3 @@
[(set_attr "type" "vecsimple")
(set_attr "prefixed" "yes")])
-;; XXSPLTIW built-in function support. Convert to a vector constant, which
-;; will then be optimized to the XXSPLTIW instruction.
-(define_expand "xxspltiw_v4si"
- [(use (match_operand:V4SI 0 "register_operand"))
- (use (match_operand:SI 1 "s32bit_cint_operand"))]
- "TARGET_POWER10"
-{
- rtx op1 = operands[1];
- rtvec rv = gen_rtvec (4, op1, op1, op1, op1);
- rtx vec_constant = gen_rtx_CONST_VECTOR (V4SImode, rv);
- emit_move_insn (operands[0], vec_constant);
-})
-
-(define_expand "xxspltiw_v4sf"
- [(use (match_operand:V4SF 0 "register_operand"))
- (use (match_operand:SF 1 "const_double_operand"))]
- "TARGET_POWER10"
-{
- rtx op1 = operands[1];
- rtvec rv = gen_rtvec (4, op1, op1, op1, op1);
- rtx vec_constant = gen_rtx_CONST_VECTOR (V4SFmode, rv);
- emit_move_insn (operands[0], vec_constant);
-})
-
-;; XXSPLTIW support. Add support for the XXSPLTIW built-in functions, and to
-;; use XXSPLTIW to load up vector V8HImode, V4SImode, and V4SFmode vector
-;; constants where all elements are the the same. We special case loading up
-;; integer -16..15 and floating point 0.0f, since we can use the shorter
-;; XXSPLTIB, VSPLTISH, and VSPLTISW instructions.
-
-(define_insn "*xxspltiw_v8hi_dup"
- [(set (match_operand:V8HI 0 "vsx_register_operand" "=wa,wa,v,wa")
- (vec_duplicate:V8HI
- (match_operand 1 "const_int_operand" "O,wM,wB,n")))]
- "TARGET_XXSPLTIW"
-{
- HOST_WIDE_INT sign_value = SIGN_EXTEND_16BIT (INTVAL (operands[1]));
-
- if (sign_value == 0)
- return "xxspltib %x0,0";
-
- if (sign_value == -1)
- return "xxspltib %x0,255";
-
- int r = reg_or_subregno (operands[0]);
- if (ALTIVEC_REGNO_P (r) && EASY_VECTOR_15 (sign_value))
- {
- operands[2] = GEN_INT (sign_value);
- return "vspltish %0,%1";
- }
-
- HOST_WIDE_INT uns_value = sign_value & 0xffff;
- operands[2] = GEN_INT ((uns_value << 16) | uns_value);
- return "xxspltiw %x0,%2";
-}
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "*,*,*,yes")])
-
-(define_insn "*xxspltiw_v4si_dup"
- [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,wa,v,wa")
- (vec_duplicate:V4SI
- (match_operand 1 "const_int_operand" "O,wM,wB,n")))]
- "TARGET_XXSPLTIW"
-{
- HOST_WIDE_INT sign_value = SIGN_EXTEND_32BIT (INTVAL (operands[1]));
-
- if (sign_value == 0)
- return "xxspltib %x0,0";
-
- if (sign_value == -1)
- return "xxspltib %x0,255";
-
- int r = reg_or_subregno (operands[0]);
- if (ALTIVEC_REGNO_P (r) && EASY_VECTOR_15 (sign_value))
- {
- operands[2] = GEN_INT (sign_value);
- return "vspltisw %0,%2";
- }
-
- /* The assembler doesn't like negative values. */
- operands[2] = GEN_INT (sign_value & 0xffffffff);
- return "xxspltiw %x0,%2";
-}
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "*,*,*,yes")])
-
-(define_insn "xxspltiw_v4sf_dup"
- [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa")
- (vec_duplicate:V4SF
- (match_operand:SF 1 "const_double_operand" "O,F")))]
- "TARGET_XXSPLTIW"
-{
- if (operands[1] == CONST0_RTX (SFmode))
- return "xxspltib %x0,0";
-
- /* The assembler doesn't like negative values. */
- long value = rs6000_const_f32_to_i32 (operands[1]);
- operands[2] = GEN_INT (value & 0xffffffff);
- return "xxspltiw %x0,%2";
-}
- [(set_attr "type" "vecsimple")
- (set_attr "prefixed" "*,yes")])
-
-;; Convert vector constant to vec_duplicate.
-(define_mode_iterator XXSPLTIW [V8HI V4SI V4SF])
-
-(define_split
- [(set (match_operand:XXSPLTIW 0 "vsx_register_operand")
- (match_operand:XXSPLTIW 1 "xxspltiw_operand"))]
- "TARGET_XXSPLTIW && GET_CODE (operands[1]) == CONST_VECTOR"
- [(set (match_dup 0)
- (vec_duplicate:<MODE> (match_dup 2)))]
-{
- operands[2] = CONST_VECTOR_ELT (operands[1], 0);
-})
-
-;; Generate the XXSPLTIDP instruction to support SFmode and DFmode scalar
-;; constants and V2DF vector constants where both elements are the same. The
-;; constant has be expressible as a SFmode constant that is not a SFmode
-;; denormal value.
-(define_mode_iterator XXSPLTIDP [SF DF V2DF])
-
-(define_insn_and_split "*xxspltidp_<mode>_internal1"
- [(set (match_operand:XXSPLTIDP 0 "vsx_register_operand" "=wa")
- (match_operand:XXSPLTIDP 1 "xxspltidp_operand"))]
- "TARGET_XXSPLTIDP"
- "#"
- "&& 1"
- [(set (match_operand:XXSPLTIDP 0 "vsx_register_operand")
- (unspec:XXSPLTIDP [(match_dup 2)] UNSPEC_XXSPLTIDP))]
-{
- HOST_WIDE_INT value = 0;
-
- if (!xxspltidp_constant_p (operands[1], <MODE>mode, &value))
- gcc_unreachable ();
-
- operands[2] = GEN_INT (value);
-}
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-;; Just in case the user issued -mno-xxspltidp, allow the built-in function
-;; even if the compiler does not automatically generate XXSPLTIDP.
-(define_insn "xxspltidp_<mode>_internal2"
- [(set (match_operand:XXSPLTIDP 0 "vsx_register_operand" "=wa")
- (unspec:XXSPLTIDP [(match_operand 1 "const_int_operand" "n")]
- UNSPEC_XXSPLTIDP))]
- "TARGET_POWER10"
- "xxspltidp %x0,%1"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-;; XXSPLTI32DX used to create 64-bit constants or vector constants where the
-;; even elements match and the odd elements match.
-(define_mode_iterator XXSPLTI32DX [SF DF V2DF V2DI])
-
-(define_insn_and_split "*xxsplti32dx_<mode>"
- [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa")
- (match_operand:XXSPLTI32DX 1 "xxsplti32dx_operand"))]
- "TARGET_XXSPLTI32DX"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (unspec:XXSPLTI32DX [(match_dup 2)
- (match_dup 3)] UNSPEC_XXSPLTI32DX_CONST))
- (set (match_dup 0)
- (unspec:XXSPLTI32DX [(match_dup 0)
- (match_dup 4)
- (match_dup 5)] UNSPEC_XXSPLTI32DX_CONST))]
-{
- HOST_WIDE_INT high = 0, low = 0;
-
- if (!xxsplti32dx_constant_p (operands[1], <MODE>mode, &high, &low))
- gcc_unreachable ();
-
- /* If the low bits are 0 or all 1s, initialize that word first. This way we
- can use a smaller XXSPLTIB instruction instead the first XXSPLTI32DX. */
- if (low == 0 || low == -1)
- {
- operands[2] = const1_rtx;
- operands[3] = GEN_INT (low);
- operands[4] = const0_rtx;
- operands[5] = GEN_INT (high);
- }
- else
- {
- operands[2] = const0_rtx;
- operands[3] = GEN_INT (high);
- operands[4] = const1_rtx;
- operands[5] = GEN_INT (low);
- }
-}
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")
- (set_attr "num_insns" "2")
- (set_attr "max_prefixed_insns" "2")])
-
-;; First word of XXSPLTI32DX
-(define_insn "*xxsplti32dx_<mode>_first"
- [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa,wa,wa")
- (unspec:XXSPLTI32DX [(match_operand 1 "u1bit_cint_operand" "n,n,n")
- (match_operand 2 "const_int_operand" "O,wM,n")]
- UNSPEC_XXSPLTI32DX_CONST))]
- "TARGET_XXSPLTI32DX"
- "@
- xxspltib %x0,0
- xxspltib %x0,255
- xxsplti32dx %x0,%1,%2"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "*,*,yes")])
-
-;; Second word of XXSPLTI32DX
-(define_insn "*xxsplti32dx_<mode>_second"
- [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa")
- (unspec:XXSPLTI32DX [(match_operand:XXSPLTI32DX 1 "vsx_register_operand" "0")
- (match_operand 2 "u1bit_cint_operand" "n")
- (match_operand 3 "const_int_operand" "n")]
- UNSPEC_XXSPLTI32DX_CONST))]
- "TARGET_XXSPLTI32DX"
- "xxsplti32dx %x0,%2,%3"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-constant.c b/gcc/testsuite/gcc.target/powerpc/float128-constant.c
deleted file mode 100644
index a5cbe0b477f..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/float128-constant.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/* { dg-require-effective-target ppc_float128_hw } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Test whether the LXVKQ instruction is generated to load special IEEE 128-bit
- constants. */
-
-_Float128
-return_0 (void)
-{
- return 0.0f128; /* XXSPLTIB 34,0. */
-}
-
-_Float128
-return_1 (void)
-{
- return 1.0f128; /* LXVKQ 34,1. */
-}
-
-_Float128
-return_2 (void)
-{
- return 2.0f128; /* LXVKQ 34,2. */
-}
-
-_Float128
-return_3 (void)
-{
- return 3.0f128; /* LXVKQ 34,3. */
-}
-
-_Float128
-return_4 (void)
-{
- return 4.0f128; /* LXVKQ 34,4. */
-}
-
-_Float128
-return_5 (void)
-{
- return 5.0f128; /* LXVKQ 34,5. */
-}
-
-_Float128
-return_6 (void)
-{
- return 6.0f128; /* LXVKQ 34,6. */
-}
-
-_Float128
-return_7 (void)
-{
- return 7.0f128; /* LXVKQ 34,7. */
-}
-
-_Float128
-return_m0 (void)
-{
- return -0.0f128; /* LXVKQ 34,16. */
-}
-
-_Float128
-return_m1 (void)
-{
- return -1.0f128; /* LXVKQ 34,17. */
-}
-
-_Float128
-return_m2 (void)
-{
- return -2.0f128; /* LXVKQ 34,18. */
-}
-
-_Float128
-return_m3 (void)
-{
- return -3.0f128; /* LXVKQ 34,19. */
-}
-
-_Float128
-return_m4 (void)
-{
- return -4.0f128; /* LXVKQ 34,20. */
-}
-
-_Float128
-return_m5 (void)
-{
- return -5.0f128; /* LXVKQ 34,21. */
-}
-
-_Float128
-return_m6 (void)
-{
- return -6.0f128; /* LXVKQ 34,22. */
-}
-
-_Float128
-return_m7 (void)
-{
- return -7.0f128; /* LXVKQ 34,23. */
-}
-
-_Float128
-return_inf (void)
-{
- return __builtin_inff128 (); /* LXVKQ 34,8. */
-}
-
-_Float128
-return_minf (void)
-{
- return - __builtin_inff128 (); /* LXVKQ 34,24. */
-}
-
-_Float128
-return_nan (void)
-{
- return __builtin_nanf128 (""); /* LXVKQ 34,9. */
-}
-
-/* Note, the following NaNs should not generate a LXVKQ instruction. */
-_Float128
-return_mnan (void)
-{
- return - __builtin_nanf128 (""); /* PLXV 34,... */
-}
-
-_Float128
-return_nan2 (void)
-{
- return __builtin_nanf128 ("1"); /* PLXV 34,... */
-}
-
-_Float128
-return_nans (void)
-{
- return __builtin_nansf128 (""); /* PLXV 34,... */
-}
-
-/* { dg-final { scan-assembler-times {\mlxvkq\M} 18 } } */
-/* { dg-final { scan-assembler-times {\mplxv\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 1 } } */
-
diff --git a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv.c b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv.c
index 22e43d21565..f312550f04d 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv.c
@@ -57,12 +57,7 @@ vector signed int splats3(void)
If folding is enabled, the vec_sl tests using vector long long type will
generate a lvx instead of a vspltisw+vsld pair. */
-/* { dg-final { scan-assembler-times {\mvspltis[bhw]\M|\mxxspltib\M} 7 { target { ! has_arch_pwr10 } } } } */
-/* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 7 { target { ! has_arch_pwr10 } } } } */
-
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 2 { target { has_arch_pwr10 } } } } */
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 5 { target { has_arch_pwr10 } } } } */
-/* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 2 { target { has_arch_pwr10 } } } } */
-
+/* { dg-final { scan-assembler-times {\mvspltis[bhw]\M|\mxxspltib\M} 7 } } */
+/* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 7 } } */
/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M} 0 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-const.c b/gcc/testsuite/gcc.target/powerpc/prefix-large-const.c
deleted file mode 100644
index df0e333d148..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/prefix-large-const.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_prefixed_addr } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
-
-/* Test whether we can use PLI/PADDI to load up large constants. */
-
-long
-foo_1 (void)
-{
- return 1L << 53; /* LIS, SLDI. */
-}
-
-long
-foo_2 (void)
-{
- return 1L << 34; /* LI, SLDI. */
-}
-
-long
-foo_3 (void)
-{
- return (1L << 53) | (1L << 35); /* PLI, SLDI. */
-}
-
-long
-foo_4 (void)
-{
- return ((1L << 53) /* PLI, SLDI, PADDI. */
- | (1L << 35)
- | (1L << 30)
- | (1L << 2));
-}
-
-long
-foo_5 (void)
-{
- return ((1L << 53) /* PLI, SLDI, ORI. */
- | (1L << 35)
- | (1L << 2));
-}
-
-long
-foo_6 (void)
-{
- return ((1L << 53) /* PLI, SLDI, ORIS. */
- | (1L << 35)
- | (1L << 30));
-}
-
-/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlis\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mori\M} 1 } } */
-/* { dg-final { scan-assembler-times {\moris\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mpaddi\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mpli\M} 4 } } */
-/* { dg-final { scan-assembler-times {\msldi\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
deleted file mode 100644
index 1435ef4ef4f..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-double
-scalar_double_0 (void)
-{
- return 0.0; /* XXSPLTIB or XXLXOR. */
-}
-
-double
-scalar_double_1 (void)
-{
- return 1.0; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-double
-scalar_double_m0 (void)
-{
- return -0.0; /* XXSPLTIDP. */
-}
-
-double
-scalar_double_nan (void)
-{
- return __builtin_nan (""); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_inf (void)
-{
- return __builtin_inf (); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inf ();
-}
-#endif
-
-double
-scalar_double_pi (void)
-{
- return M_PI; /* 2x XXSPLTI32DX. */
-}
-
-double
-scalar_double_denorm (void)
-{
- return 0x1p-149f; /* XXSPLTIB, XXSPLTI32DX. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
-/* { dg-final { scan-assembler-not {\mplfd\M} } } */
-/* { dg-final { scan-assembler-not {\mplxsd\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
deleted file mode 100644
index e9a45d5159d..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating SFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-float
-scalar_float_0 (void)
-{
- return 0.0f; /* XXSPLTIB or XXLXOR. */
-}
-
-float
-scalar_float_1 (void)
-{
- return 1.0f; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-float
-scalar_float_m0 (void)
-{
- return -0.0f; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_nan (void)
-{
- return __builtin_nanf (""); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_inf (void)
-{
- return __builtin_inff (); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inff ();
-}
-#endif
-
-float
-scalar_float_pi (void)
-{
- return (float)M_PI; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_denorm (void)
-{
- return 0x1p-149f; /* PLFS. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mplfs\M} } } */
-/* { dg-final { scan-assembler-not {\mplxssp\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
deleted file mode 100644
index d81198b163d..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating V2DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-vector double
-v2df_double_0 (void)
-{
- return (vector double) { 0.0, 0.0 }; /* XXSPLTIB or XXLXOR. */
-}
-
-vector double
-v2df_double_1 (void)
-{
- return (vector double) { 1.0, 1.0 }; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-vector double
-v2df_double_m0 (void)
-{
- return (vector double) { -0.0, -0.0 }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_nan (void)
-{
- return (vector double) { __builtin_nan (""),
- __builtin_nan ("") }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_inf (void)
-{
- return (vector double) { __builtin_inf (),
- __builtin_inf () }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_m_inf (void)
-{
- return (vector double) { - __builtin_inf (),
- - __builtin_inf () }; /* XXSPLTIDP. */
-}
-#endif
-
-vector double
-v2df_double_pi (void)
-{
- return (vector double) { M_PI, M_PI }; /* 2x XXSPLTI32DX. */
-}
-
-vector double
-v2df_double_denorm (void)
-{
- return (vector double) { (double)0x1p-149f, /* XXSPLTIB, */
- (double)0x1p-149f }; /* XXSPLTI32DX. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
deleted file mode 100644
index 06830b02076..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SF vector constants. */
-
-vector float
-v4sf_const_1 (void)
-{
- return (vector float) { 1.0f, 1.0f, 1.0f, 1.0f }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_nan (void)
-{
- return (vector float) { __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf ("") }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_inf (void)
-{
- return (vector float) { __builtin_inff (),
- __builtin_inff (),
- __builtin_inff (),
- __builtin_inff () }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_m0 (void)
-{
- return (vector float) { -0.0f, -0.0f, -0.0f, -0.0f }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_1 (void)
-{
- return vec_splats (1.0f); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_nan (void)
-{
- return vec_splats (__builtin_nanf ("")); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_inf (void)
-{
- return vec_splats (__builtin_inff ()); /* XXSPLTIW. */
-}
-
-vector float
-v8hi_splats_m0 (void)
-{
- return vec_splats (-0.0f); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 8 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
deleted file mode 100644
index 02d0c6d66a2..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SI vector constants. We make sure
- the power9 support (XXSPLTIB/VEXTSB2W) is not done. */
-
-vector int
-v4si_const_1 (void)
-{
- return (vector int) { 1, 1, 1, 1 }; /* VSLTPISW. */
-}
-
-vector int
-v4si_const_126 (void)
-{
- return (vector int) { 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_const_1023 (void)
-{
- return (vector int) { 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_splats_1 (void)
-{
- return vec_splats (1); /* VSLTPISW. */
-}
-
-vector int
-v4si_splats_126 (void)
-{
- return vec_splats (126); /* XXSPLTIW. */
-}
-
-vector int
-v8hi_splats_1023 (void)
-{
- return vec_splats (1023); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mvspltisw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvextsb2w\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
deleted file mode 100644
index e6d0fab6d67..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V8HI vector constants. We make sure
- the power9 support (XXSPLTIB/VUPKLSB) is not done. */
-
-vector short
-v8hi_const_1 (void)
-{
- return (vector short) { 1, 1, 1, 1, 1, 1, 1, 1 }; /* VSLTPISH. */
-}
-
-vector short
-v8hi_const_126 (void)
-{
- return (vector short) { 126, 126, 126, 126,
- 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_const_1023 (void)
-{
- return (vector short) { 1023, 1023, 1023, 1023,
- 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1 (void)
-{
- return vec_splats ((short)1); /* VSLTPISH. */
-}
-
-vector short
-v8hi_splats_126 (void)
-{
- return vec_splats ((short)126); /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1023 (void)
-{
- return vec_splats ((short)1023); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mvspltish\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvupklsb\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
index f49ef91422e..a135279b1d7 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
@@ -149,6 +149,8 @@ main (int argc, char *argv [])
return 0;
}
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxxspltiw\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
+
+
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