[gcc r12-2629] mips: add MSA vec_cmp and vec_cmpu expand pattern [PR101132]

[gcc r12-2629] mips: add MSA vec_cmp and vec_cmpu expand pattern [PR101132]

[Xi Ruoyao]

https://gcc.gnu.org/g:45cb789e6adf5d571c574a94b77413c845fed106

commit r12-2629-g45cb789e6adf5d571c574a94b77413c845fed106
Author: Xi Ruoyao <xry111@mengyan1223.wang>
Date:   Sun Jun 20 15:21:39 2021 +0800

    mips: add MSA vec_cmp and vec_cmpu expand pattern [PR101132]
    
    Middle-end started to emit vec_cmp and vec_cmpu since GCC 11, causing
    ICE on MIPS with MSA enabled.  Add the pattern to prevent it.
    
    gcc/
    
            PR target/101132
            * config/mips/mips-protos.h (mips_expand_vec_cmp_expr): Declare.
            * config/mips/mips.c (mips_expand_vec_cmp_expr): New function.
            * config/mips/mips-msa.md (vec_cmp<MSA:mode><mode_i>): New
              expander.
              (vec_cmpu<IMSA:mode><mode_i>): New expander.
    
    gcc/testsuite/
    
            PR target/101132
            * gcc.target/mips/pr101132.c: New test.

Diff:
---
 gcc/config/mips/mips-msa.md              | 22 ++++++++++++++++++++++
 gcc/config/mips/mips-protos.h            |  1 +
 gcc/config/mips/mips.c                   | 11 +++++++++++
 gcc/testsuite/gcc.target/mips/pr101132.c | 14 ++++++++++++++
 4 files changed, 48 insertions(+)

diff --git a/gcc/config/mips/mips-msa.md b/gcc/config/mips/mips-msa.md
index 3ecf2bde19f..3a67f25be56 100644
--- a/gcc/config/mips/mips-msa.md
+++ b/gcc/config/mips/mips-msa.md
@@ -435,6 +435,28 @@
   DONE;
 })
 
+(define_expand "vec_cmp<MSA:mode><mode_i>"
+  [(match_operand:<VIMODE> 0 "register_operand")
+   (match_operator 1 ""
+     [(match_operand:MSA 2 "register_operand")
+      (match_operand:MSA 3 "register_operand")])]
+  "ISA_HAS_MSA"
+{
+  mips_expand_vec_cmp_expr (operands);
+  DONE;
+})
+
+(define_expand "vec_cmpu<IMSA:mode><mode_i>"
+  [(match_operand:<VIMODE> 0 "register_operand")
+   (match_operator 1 ""
+     [(match_operand:IMSA 2 "register_operand")
+      (match_operand:IMSA 3 "register_operand")])]
+  "ISA_HAS_MSA"
+{
+  mips_expand_vec_cmp_expr (operands);
+  DONE;
+})
+
 (define_insn "msa_insert_<msafmt_f>"
   [(set (match_operand:MSA 0 "register_operand" "=f,f")
 	(vec_merge:MSA
diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h
index 51b82b1458d..a5e4151b9e6 100644
--- a/gcc/config/mips/mips-protos.h
+++ b/gcc/config/mips/mips-protos.h
@@ -385,6 +385,7 @@ extern mulsidi3_gen_fn mips_mulsidi3_gen_fn (enum rtx_code);
 
 extern void mips_register_frame_header_opt (void);
 extern void mips_expand_vec_cond_expr (machine_mode, machine_mode, rtx *);
+extern void mips_expand_vec_cmp_expr (rtx *);
 
 /* Routines implemented in mips-d.c  */
 extern void mips_d_target_versions (void);
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 00a8eef96aa..8f043399a8e 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -22321,6 +22321,17 @@ mips_expand_msa_cmp (rtx dest, enum rtx_code cond, rtx op0, rtx op1)
     }
 }
 
+void
+mips_expand_vec_cmp_expr (rtx *operands)
+{
+  rtx cond = operands[1];
+  rtx op0 = operands[2];
+  rtx op1 = operands[3];
+  rtx res = operands[0];
+
+  mips_expand_msa_cmp (res, GET_CODE (cond), op0, op1);
+}
+
 /* Expand VEC_COND_EXPR, where:
    MODE is mode of the result
    VIMODE equivalent integer mode
diff --git a/gcc/testsuite/gcc.target/mips/pr101132.c b/gcc/testsuite/gcc.target/mips/pr101132.c
new file mode 100644
index 00000000000..d490b5d3a82
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/pr101132.c
@@ -0,0 +1,14 @@
+/* PR target/101132
+   This was triggering an ICE in do_store_flag when compiled with -mmsa -O3. */
+
+/* { dg-do compile } */
+/* { dg-options "-mmsa" } */
+
+int r_0, q_0;
+void bar() {
+  int i;
+  for (i = 0; i < 96; i++) {
+    r_0 = i << i ? 2 + i : -i;
+    q_0 = r_0 > 2 ?: i;
+  }
+}