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* [gcc r11-8903] arm: add erratum mitigation to __gnu_cmse_nonsecure_call [PR102035]
@ 2021-08-24 13:33 Richard Earnshaw
0 siblings, 0 replies; only message in thread
From: Richard Earnshaw @ 2021-08-24 13:33 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:2539763c89a6777502f16457269e2c31d6d95b67
commit r11-8903-g2539763c89a6777502f16457269e2c31d6d95b67
Author: Richard Earnshaw <rearnsha@arm.com>
Date: Fri Jun 18 17:16:25 2021 +0100
arm: add erratum mitigation to __gnu_cmse_nonsecure_call [PR102035]
Add the recommended erratum mitigation sequence to
__gnu_cmse_nonsecure_call for use on Armv8-m.main devices. Since this
is in the library code we cannot know in advance whether the core we
are running on will be affected by this, so always enable it.
libgcc:
PR target/102035
* config/arm/cmse_nonsecure_call.S (__gnu_cmse_nonsecure_call):
Add vlldm erratum work-around.
(cherry picked from commit 574e7950bd6b34e9e2cacce18c802b45505d1d0a)
Diff:
---
libgcc/config/arm/cmse_nonsecure_call.S | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/libgcc/config/arm/cmse_nonsecure_call.S b/libgcc/config/arm/cmse_nonsecure_call.S
index 00830ade98e..c8e0fbbe665 100644
--- a/libgcc/config/arm/cmse_nonsecure_call.S
+++ b/libgcc/config/arm/cmse_nonsecure_call.S
@@ -102,6 +102,11 @@ blxns r4
#ifdef __ARM_PCS_VFP
vpop.f64 {d8-d15}
#else
+/* VLLDM erratum mitigation sequence. */
+mrs r5, control
+tst r5, #8 /* CONTROL_S.SFPA */
+it ne
+.inst.w 0xeeb00a40 /* vmovne s0, s0 */
vlldm sp /* Lazy restore of d0-d16 and FPSCR. */
add sp, sp, #0x88 /* Free space used to save floating point registers. */
#endif /* __ARM_PCS_VFP */
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