public inbox for gcc-cvs@sourceware.org
help / color / mirror / Atom feed
* [gcc r11-8924] i386: Fix _mm512_fpclass_ps_mask in O0 [PR 101471]
@ 2021-08-25 7:15 hongtao Liu
0 siblings, 0 replies; only message in thread
From: hongtao Liu @ 2021-08-25 7:15 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:6604b336517463f9189e1c95db405a154aa7c815
commit r11-8924-g6604b336517463f9189e1c95db405a154aa7c815
Author: konglin1 <lingling.kong@intel.com>
Date: Mon Aug 9 10:58:24 2021 +0800
i386: Fix _mm512_fpclass_ps_mask in O0 [PR 101471]
gcc/ChangeLog:
PR target/101471
* config/i386/avx512dqintrin.h (_mm512_fpclass_ps_mask): Fix
macro define in O0.
(_mm512_mask_fpclass_ps_mask): Ditto.
gcc/testsuite/ChangeLog:
PR target/101471
* gcc.target/i386/avx512f-pr101471.c: New test.
Diff:
---
gcc/config/i386/avx512dqintrin.h | 4 ++--
gcc/testsuite/gcc.target/i386/avx512f-pr101471.c | 18 ++++++++++++++++++
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/gcc/config/i386/avx512dqintrin.h b/gcc/config/i386/avx512dqintrin.h
index 51c0b1249ae..9794f5d3e8b 100644
--- a/gcc/config/i386/avx512dqintrin.h
+++ b/gcc/config/i386/avx512dqintrin.h
@@ -2814,7 +2814,7 @@ _mm512_fpclass_ps_mask (__m512 __A, const int __imm)
#define _mm512_mask_fpclass_ps_mask(u, x, c) \
((__mmask16) __builtin_ia32_fpclassps512_mask ((__v16sf) (__m512) (x),\
- (int) (c),(__mmask8)(u)))
+ (int) (c),(__mmask16)(u)))
#define _mm512_fpclass_pd_mask(X, C) \
((__mmask8) __builtin_ia32_fpclasspd512_mask ((__v8df) (__m512d) (X), \
@@ -2822,7 +2822,7 @@ _mm512_fpclass_ps_mask (__m512 __A, const int __imm)
#define _mm512_fpclass_ps_mask(x, c) \
((__mmask16) __builtin_ia32_fpclassps512_mask ((__v16sf) (__m512) (x),\
- (int) (c),(__mmask8)-1))
+ (int) (c),(__mmask16)-1))
#define _mm_reduce_sd(A, B, C) \
((__m128d) __builtin_ia32_reducesd_mask ((__v2df)(__m128d)(A), \
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-pr101471.c b/gcc/testsuite/gcc.target/i386/avx512f-pr101471.c
new file mode 100644
index 00000000000..4a0057b241e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-pr101471.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512dq -O0" } */
+/* { dg-require-effective-target avx512dq } */
+
+#include "avx512f-check.h"
+
+static void
+avx512f_test (void)
+{
+ __m512 x = {
+ 1, 1, 1, 1,
+ 1, 1, 1, 1,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0, };
+ int ret = _mm512_fpclass_ps_mask(x, 0x26);
+ if (ret != 65280)
+ __builtin_abort();
+}
^ permalink raw reply [flat|nested] only message in thread
only message in thread, other threads:[~2021-08-25 7:15 UTC | newest]
Thread overview: (only message) (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-08-25 7:15 [gcc r11-8924] i386: Fix _mm512_fpclass_ps_mask in O0 [PR 101471] hongtao Liu
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).