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* [gcc r12-3137] i386: Optimize lea with zero-extend. [PR 101716]
@ 2021-08-25 9:04 Hongyu Wang
0 siblings, 0 replies; only message in thread
From: Hongyu Wang @ 2021-08-25 9:04 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:87afc7b81cd44d04997add383856b2504af3afe6
commit r12-3137-g87afc7b81cd44d04997add383856b2504af3afe6
Author: Hongyu Wang <hongyu.wang@intel.com>
Date: Tue Aug 17 16:53:46 2021 +0800
i386: Optimize lea with zero-extend. [PR 101716]
For ASHIFT + ZERO_EXTEND pattern, combine pass failed to
match it to lea since it will generate non-canonical
zero-extend. Adjust predicate and cost_model to allow combine
for lea.
gcc/ChangeLog:
PR target/101716
* config/i386/i386.c (ix86_live_on_entry): Adjust comment.
(ix86_decompose_address): Remove retval check for ASHIFT,
allow non-canonical zero extend if AND mask covers ASHIFT
count.
(ix86_legitimate_address_p): Adjust condition for decompose.
(ix86_rtx_costs): Adjust cost for lea with non-canonical
zero-extend.
Co-Authored by: Uros Bizjak <ubizjak@gmail.com>
gcc/testsuite/ChangeLog:
PR target/101716
* gcc.target/i386/pr101716.c: New test.
Diff:
---
gcc/config/i386/i386.c | 36 ++++++++++++++++++++++++++------
gcc/testsuite/gcc.target/i386/pr101716.c | 11 ++++++++++
2 files changed, 41 insertions(+), 6 deletions(-)
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index ebec8668758..ddbbbceded1 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -10018,8 +10018,7 @@ ix86_live_on_entry (bitmap regs)
\f
/* Extract the parts of an RTL expression that is a valid memory address
for an instruction. Return 0 if the structure of the address is
- grossly off. Return -1 if the address contains ASHIFT, so it is not
- strictly valid, but still used for computing length of lea instruction. */
+ grossly off. */
int
ix86_decompose_address (rtx addr, struct ix86_address *out)
@@ -10029,7 +10028,6 @@ ix86_decompose_address (rtx addr, struct ix86_address *out)
HOST_WIDE_INT scale = 1;
rtx scale_rtx = NULL_RTX;
rtx tmp;
- int retval = 1;
addr_space_t seg = ADDR_SPACE_GENERIC;
/* Allow zero-extended SImode addresses,
@@ -10053,6 +10051,27 @@ ix86_decompose_address (rtx addr, struct ix86_address *out)
if (CONST_INT_P (addr))
return 0;
}
+ else if (GET_CODE (addr) == AND)
+ {
+ /* For ASHIFT inside AND, combine will not generate
+ canonical zero-extend. Merge mask for AND and shift_count
+ to check if it is canonical zero-extend. */
+ tmp = XEXP (addr, 0);
+ rtx mask = XEXP (addr, 1);
+ if (tmp && GET_CODE(tmp) == ASHIFT)
+ {
+ rtx shift_val = XEXP (tmp, 1);
+ if (CONST_INT_P (mask) && CONST_INT_P (shift_val)
+ && (((unsigned HOST_WIDE_INT) INTVAL(mask)
+ | ((HOST_WIDE_INT_1U << INTVAL(shift_val)) - 1))
+ == 0xffffffff))
+ {
+ addr = lowpart_subreg (SImode, XEXP (addr, 0),
+ DImode);
+ }
+ }
+
+ }
}
/* Allow SImode subregs of DImode addresses,
@@ -10179,7 +10198,6 @@ ix86_decompose_address (rtx addr, struct ix86_address *out)
if ((unsigned HOST_WIDE_INT) scale > 3)
return 0;
scale = 1 << scale;
- retval = -1;
}
else
disp = addr; /* displacement */
@@ -10252,7 +10270,7 @@ ix86_decompose_address (rtx addr, struct ix86_address *out)
out->scale = scale;
out->seg = seg;
- return retval;
+ return 1;
}
\f
/* Return cost of the memory address x.
@@ -10765,7 +10783,7 @@ ix86_legitimate_address_p (machine_mode, rtx addr, bool strict)
HOST_WIDE_INT scale;
addr_space_t seg;
- if (ix86_decompose_address (addr, &parts) <= 0)
+ if (ix86_decompose_address (addr, &parts) == 0)
/* Decomposition failed. */
return false;
@@ -20419,6 +20437,12 @@ ix86_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
<< (GET_MODE (XEXP (x, 1)) != DImode)));
return true;
}
+ else if (code == AND
+ && address_no_seg_operand (x, mode))
+ {
+ *total = cost->lea;
+ return true;
+ }
/* FALLTHRU */
case NEG:
diff --git a/gcc/testsuite/gcc.target/i386/pr101716.c b/gcc/testsuite/gcc.target/i386/pr101716.c
new file mode 100644
index 00000000000..5e3ea64a320
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr101716.c
@@ -0,0 +1,11 @@
+/* PR target/101716 */
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2" } */
+
+/* { dg-final { scan-assembler "leal\[\\t \]\[^\\n\]*eax" } } */
+/* { dg-final { scan-assembler-not "movl\[\\t \]\[^\\n\]*eax" } } */
+
+unsigned long long sample1(unsigned long long m) {
+ unsigned int t = -1;
+ return (m << 1) & t;
+}
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