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* [gcc(refs/users/meissner/heads/work067)] Revert patches.
@ 2021-09-08 18:57 Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2021-09-08 18:57 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:f3b52f3d0ad38a9029dc9a0b06c480975251bba2
commit f3b52f3d0ad38a9029dc9a0b06c480975251bba2
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Sep 8 14:56:42 2021 -0400
Revert patches.
2021-09-08 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patch.
* config/rs6000/rs6000.c (rs6000_emit_move_si_sf_subreg): Deal
with SUBREGs of TImode and DImode.
* config/rs6000/rs6000.md (SI_DI_TI): New mode iterator.
(movsf_from_<mode>): Replace movsf_from_si to add support for
subregs of DImode and TImode.
2021-09-06 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patch.
* config/rs6000/rs6000.c (rs6000_emit_move_si_sf_subreg): Deal
with SUBREGs of TImode and DImode.
Diff:
---
gcc/config/rs6000/rs6000.c | 15 ++++++---------
gcc/config/rs6000/rs6000.md | 15 +++++----------
2 files changed, 11 insertions(+), 19 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index bd1ae1f8d6e..7bbf29a3e1c 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -10942,16 +10942,13 @@ rs6000_emit_move_si_sf_subreg (rtx dest, rtx source, machine_mode mode)
return true;
}
- /* Deal with subregs of SI/DI/TImode. */
- if (mode == SFmode && inner_mode == TImode)
+ /* In case we are given a SUBREG for a larger type, reduce it to
+ SImode. */
+ if (mode == SFmode && GET_MODE_SIZE (inner_mode) > 4)
{
- emit_insn (gen_movsf_from_ti (dest, inner_source));
- return true;
- }
-
- if (mode == SFmode && inner_mode == DImode)
- {
- emit_insn (gen_movsf_from_di (dest, inner_source));
+ rtx tmp = gen_reg_rtx (SImode);
+ emit_move_insn (tmp, gen_lowpart (SImode, source));
+ emit_insn (gen_movsf_from_si (dest, tmp));
return true;
}
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index fd3f6043e4b..d6af66a1728 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -466,9 +466,6 @@
; Any supported integer mode.
(define_mode_iterator INT [QI HI SI DI TI PTI])
-; Any supported integer mode that is at least 32-bits in size.
-(define_mode_iterator SI_DI_TI [SI DI TI])
-
; Any supported integer mode that fits in one register.
(define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
@@ -7864,11 +7861,11 @@
;; LWZ LFS LXSSP LXSSPX STW STFIWX
;; STXSIWX GPR->VSX VSX->GPR GPR->GPR
-(define_insn_and_split "movsf_from_<mode>"
+(define_insn_and_split "movsf_from_si"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, Z,
Z, wa, ?r, !r")
- (unspec:SF [(match_operand:SI_DI_TI 1 "input_operand"
+ (unspec:SF [(match_operand:SI 1 "input_operand"
"m, m, wY, Z, r, f,
wa, r, wa, r")]
UNSPEC_SF_FROM_SI))
@@ -7877,7 +7874,7 @@
X, r, X, X"))]
"TARGET_NO_SF_SUBREG
&& (register_operand (operands[0], SFmode)
- || register_operand (operands[1], <MODE>mode))"
+ || register_operand (operands[1], SImode))"
"@
lwz%U1%X1 %0,%1
lfs%U1%X1 %0,%1
@@ -7892,15 +7889,13 @@
"&& reload_completed
&& vsx_reg_sfsubreg_ok (operands[0], SFmode)
- && int_reg_operand_not_pseudo (operands[1], <MODE>mode)"
+ && int_reg_operand_not_pseudo (operands[1], SImode)"
[(const_int 0)]
{
rtx op0 = operands[0];
rtx op1 = operands[1];
rtx op2 = operands[2];
- rtx op1_di = ((<MODE>mode == SImode)
- ? gen_rtx_REG (DImode, reg_or_subregno (op1))
- : gen_lowpart (DImode, op1));
+ rtx op1_di = gen_rtx_REG (DImode, REGNO (op1));
/* Move SF value to upper 32-bits for xscvspdpn. */
emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));
^ permalink raw reply [flat|nested] 4+ messages in thread
* [gcc(refs/users/meissner/heads/work067)] Revert patches.
@ 2021-09-08 19:06 Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2021-09-08 19:06 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:020574404a3b397e575e71c2e97d121b8cec6a3b
commit 020574404a3b397e575e71c2e97d121b8cec6a3b
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Sep 8 15:05:50 2021 -0400
Revert patches.
2021-09-08 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/rs6000.c (rs6000_emit_move_si_sf_subreg): Deal
with SUBREGs of TImode and DImode.
* config/rs6000/rs6000.md (SI_DI_TI): New mode iterator.
(movsf_from_<mode>): Replace movsf_from_si to add support for
subregs of DImode and TImode.
2021-09-06 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/rs6000.c (rs6000_emit_move_si_sf_subreg): Deal
with SUBREGs of TImode and DImode.
Diff:
---
gcc/config/rs6000/rs6000.c | 13 -------------
gcc/config/rs6000/rs6000.md | 15 +++++----------
2 files changed, 5 insertions(+), 23 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index bd1ae1f8d6e..b9ebd56c993 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -10942,19 +10942,6 @@ rs6000_emit_move_si_sf_subreg (rtx dest, rtx source, machine_mode mode)
return true;
}
- /* Deal with subregs of SI/DI/TImode. */
- if (mode == SFmode && inner_mode == TImode)
- {
- emit_insn (gen_movsf_from_ti (dest, inner_source));
- return true;
- }
-
- if (mode == SFmode && inner_mode == DImode)
- {
- emit_insn (gen_movsf_from_di (dest, inner_source));
- return true;
- }
-
if (mode == SFmode && inner_mode == SImode)
{
emit_insn (gen_movsf_from_si (dest, inner_source));
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index fd3f6043e4b..d6af66a1728 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -466,9 +466,6 @@
; Any supported integer mode.
(define_mode_iterator INT [QI HI SI DI TI PTI])
-; Any supported integer mode that is at least 32-bits in size.
-(define_mode_iterator SI_DI_TI [SI DI TI])
-
; Any supported integer mode that fits in one register.
(define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
@@ -7864,11 +7861,11 @@
;; LWZ LFS LXSSP LXSSPX STW STFIWX
;; STXSIWX GPR->VSX VSX->GPR GPR->GPR
-(define_insn_and_split "movsf_from_<mode>"
+(define_insn_and_split "movsf_from_si"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, Z,
Z, wa, ?r, !r")
- (unspec:SF [(match_operand:SI_DI_TI 1 "input_operand"
+ (unspec:SF [(match_operand:SI 1 "input_operand"
"m, m, wY, Z, r, f,
wa, r, wa, r")]
UNSPEC_SF_FROM_SI))
@@ -7877,7 +7874,7 @@
X, r, X, X"))]
"TARGET_NO_SF_SUBREG
&& (register_operand (operands[0], SFmode)
- || register_operand (operands[1], <MODE>mode))"
+ || register_operand (operands[1], SImode))"
"@
lwz%U1%X1 %0,%1
lfs%U1%X1 %0,%1
@@ -7892,15 +7889,13 @@
"&& reload_completed
&& vsx_reg_sfsubreg_ok (operands[0], SFmode)
- && int_reg_operand_not_pseudo (operands[1], <MODE>mode)"
+ && int_reg_operand_not_pseudo (operands[1], SImode)"
[(const_int 0)]
{
rtx op0 = operands[0];
rtx op1 = operands[1];
rtx op2 = operands[2];
- rtx op1_di = ((<MODE>mode == SImode)
- ? gen_rtx_REG (DImode, reg_or_subregno (op1))
- : gen_lowpart (DImode, op1));
+ rtx op1_di = gen_rtx_REG (DImode, REGNO (op1));
/* Move SF value to upper 32-bits for xscvspdpn. */
emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));
^ permalink raw reply [flat|nested] 4+ messages in thread
* [gcc(refs/users/meissner/heads/work067)] Revert patches.
@ 2021-09-07 2:09 Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2021-09-07 2:09 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:855679edef5640a1e41bd1fc2180b5406dc3a6c0
commit 855679edef5640a1e41bd1fc2180b5406dc3a6c0
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Sep 6 22:08:16 2021 -0400
Revert patches.
2021-09-06 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patch.
* config/rs6000/constraint.md (eD): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): If the constant
can be loaded with XXSPLTI32DX, it is easy.
(xxsplti32dx_operand): New predicate.
(easy_vector_constant): If the constant can be loaded with
XXSPLTI32DX, it is easy.
* config/rs6000/rs6000-protos.h (xxsplti32dx_constant_p): New
declaration.
* config/rs6000/rs6000.c (xxsplti32dx_constant_float_p): New
helper function.
(xxsplti32dx_constant_p): New function.
(output_vec_const_move): If the operand can be loaded with
XXSPLTI32DX, split it.
(prefixed_permute_p): Constants loaded with XXSPLTI32DX are
prefixed.
* config/rs6000/rs6000.md (movsf_hardfloat): Add support for
constants loaded with XXSPLTI32DX.
(mov<mode>_hardfloat32, FMOVE64 iterator): Add support for
constants loaded with XXSPLTI32DX.
(mov<mode>_hardfloat64, FMOVE64 iterator): Add support for
constants loaded with XXSPLTI32DX.
* config/rs6000/rs6000.opt (-mxxsplti32dx): New option.
* config/rs6000/vsx.md (UNSPEC_XXSPLTI32DX_CONST): New unspec.
(XXSPLTI32DX): New mode iterator.
(xxsplti32dx_<mode>): New insn and splitter for XXSPLTI32DX.
(xxsplti32dx_<mode>_first): New insn.
(xxsplti32dx_<mode>_second): New insn.
gcc/testsuite/
Revert patch.
* gcc.target/powerpc/pr86731-fwrapv-longlong.c: Update insn
count.
* gcc.target/powerpc/vec-splat-constant-sf.c: Update insn count.
Add -mxxsplti32dx option.
* gcc.target/powerpc/vec-splat-constant-df.c: Likewise.
* gcc.target/powerpc/vec-splat-constant-v2df.c: Likewise.
gcc/
Revert patch.
* config/rs6000/constraints.md (eW): New constraint.
* config/rs6000/predicates.md (xxspltiw_operand): New predicate.
(easy_vector_constant): If we can use XXSPLTIW, the vector
constant is easy.
* config/rs6000/rs6000-protos.h (xxspltiw_constant_p): New
declaration.
* config/rs6000/rs6000.c (xxspltib_constant_p): If we can generate
XXSPLTIW, don't generate a XXSPLTIB and an extend instruction.
(const_vector_all_elements_equal_p): New function.
(xxspltiw_constant_p): New function.
(output_vec_const_move): Add support for loading up vector
constants with XXSPLTIW.
(prefixed_permute_p): Recognize xxspltiw instructions as
prefixed.
* config/rs6000/rs6000.opt (-mxxspltiw): New debug switch.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
constants loaded with XXSPLTIW.
(vsx_mov<mode>_32bit): Likewise.
(vsx_splat_v8hi_xxspltiw): New insn.
(vsx_splat_v4si_xxspltiw): New insn.
(vsx_splat_v4sf_xxspltiw): New insn.
gcc/testsuite/
Revert patch.
* gcc.target/powerpc/vec-splat-constant-v16qi.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4si.c: New test.
* gcc.target/powerpc/vec-splat-constant-v8hi.c: New test.
* gcc.target/powerpc/vec-splati-runnable.c: Update insn counts.
Diff:
---
gcc/config/rs6000/constraints.md | 11 -
gcc/config/rs6000/predicates.md | 32 ---
gcc/config/rs6000/rs6000-protos.h | 3 -
gcc/config/rs6000/rs6000.c | 296 +--------------------
gcc/config/rs6000/rs6000.md | 61 ++---
gcc/config/rs6000/rs6000.opt | 10 -
gcc/config/rs6000/vsx.md | 148 +----------
.../gcc.target/powerpc/pr86731-fwrapv-longlong.c | 5 +-
.../gcc.target/powerpc/vec-splat-constant-df.c | 11 +-
.../gcc.target/powerpc/vec-splat-constant-sf.c | 7 +-
.../gcc.target/powerpc/vec-splat-constant-v16qi.c | 27 --
.../gcc.target/powerpc/vec-splat-constant-v2df.c | 10 +-
.../gcc.target/powerpc/vec-splat-constant-v4sf.c | 67 -----
.../gcc.target/powerpc/vec-splat-constant-v4si.c | 51 ----
.../gcc.target/powerpc/vec-splat-constant-v8hi.c | 62 -----
.../gcc.target/powerpc/vec-splati-runnable.c | 4 +-
16 files changed, 46 insertions(+), 759 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 6317f928dc4..4637345f84b 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -208,12 +208,6 @@
(and (match_code "const_int")
(match_test "((- (unsigned HOST_WIDE_INT) ival) + 0x8000) < 0x10000")))
-;; SF/DF/V2DF/DI/V2DI scalar or vector constant that can be loaded with a pair
-;; of XXSPLTI32DX instructions.
-(define_constraint "eD"
- "A vector constant that can be loaded with XXSPLTI32DX instructions."
- (match_operand 0 "xxsplti32dx_operand"))
-
;; SF/DF/V2DF scalar or vector constant that can be loaded with XXSPLTIDP
(define_constraint "eF"
"A vector constant that can be loaded with the XXSPLTIDP instruction."
@@ -224,11 +218,6 @@
"A signed 34-bit integer constant if prefixed instructions are supported."
(match_operand 0 "cint34_operand"))
-;; Vector constant that can be loaded with XXSPLTIW
-(define_constraint "eW"
- "A vector constant that can be loaded with the XXSPLTIW instruction."
- (match_operand 0 "xxspltiw_operand"))
-
;; KF/TF scalar than can be loaded with LXVKQ
(define_constraint "eQ"
"An IEEE 128-bit constant that can be loaded with the LXVKQ instruction."
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index a5d51f4ad84..1a87272604b 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -611,11 +611,6 @@
if (lxvkq_operand (op, mode))
return 1;
- /* If we have the ISA 3.1 XXSPLTI32DX instruction, see if the constant can
- be loaded with a pair of those instructions. */
- if (xxsplti32dx_operand (op, mode))
- return 1;
-
/* Otherwise consider floating point constants hard, so that the
constant gets pushed to memory during the early RTL phases. This
has the advantage that double precision constants that can be
@@ -655,16 +650,6 @@
return num_insns == 1;
})
-;; Return 1 if the operand is a CONST_VECTOR that can be loaded with the
-;; XXSPLTIW instruction.
-(define_predicate "xxspltiw_operand"
- (match_code "const_vector")
-{
- HOST_WIDE_INT xxspltiw_value = 0;
-
- return xxspltiw_constant_p (op, mode, &xxspltiw_value);
-})
-
;; Return 1 if operand is a SF/DF CONST_DOUBLE or V2DF CONST_VECTOR that can be
;; loaded via the ISA 3.1 XXSPLTIDP instruction.
(define_predicate "xxspltidp_operand"
@@ -683,17 +668,6 @@
return lxvkq_constant_p (op, mode, &immediate);
})
-;; Return 1 if operand is a SF/DF CONST_DOUBLE or V2DF/V2DI CONST_VECTOR that
-;; can be loaded via a pair f ISA 3.1 XXSPLTI32DX instructions. Do not return
-;; true if the value can be loaded with the XXSPLTIDP instruction or XXSPLTIB
-;; to load 0.
-(define_predicate "xxsplti32dx_operand"
- (match_code "const_double,const_vector,vec_duplicate")
-{
- HOST_WIDE_INT high = 0, low = 0;
- return xxsplti32dx_constant_p (op, mode, &high, &low);
-})
-
;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
;; vector register without using memory.
(define_predicate "easy_vector_constant"
@@ -707,15 +681,9 @@
if (zero_constant (op, mode) || all_ones_constant (op, mode))
return true;
- if (xxspltiw_operand (op, mode))
- return true;
-
if (xxspltidp_operand (op, mode))
return true;
- if (xxsplti32dx_operand (op, mode))
- return true;
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (op, mode, &num_insns, &value))
return true;
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 744b1ad73e6..de1c1ee9a8b 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -33,9 +33,6 @@ extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, int, int, int,
extern int easy_altivec_constant (rtx, machine_mode);
extern bool xxspltib_constant_p (rtx, machine_mode, int *, int *);
extern bool xxspltidp_constant_p (rtx, machine_mode, HOST_WIDE_INT *);
-extern bool xxspltiw_constant_p (rtx, machine_mode, HOST_WIDE_INT *);
-extern bool xxsplti32dx_constant_p (rtx, machine_mode, HOST_WIDE_INT *,
- HOST_WIDE_INT *);
extern bool lxvkq_constant_p (rtx, machine_mode, int *);
extern int vspltis_shifted (rtx);
extern HOST_WIDE_INT const_vector_elt_as_int (rtx, unsigned int);
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 7bbf29a3e1c..f1a19207bf3 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6583,10 +6583,6 @@ xxspltib_constant_p (rtx op,
else if (IN_RANGE (value, -1, 0))
*num_insns_ptr = 1;
- /* See if we could generate XXSPLTIW directly. */
- else if (xxspltiw_operand (op, mode))
- return false;
-
else
*num_insns_ptr = 2;
@@ -6594,164 +6590,6 @@ xxspltib_constant_p (rtx op,
return true;
}
-/* Return true if the argument is a constant vector where all elements are the
- same. */
-
-static bool
-const_vector_all_elements_equal_p (rtx op, machine_mode mode)
-{
- if (!CONST_VECTOR_P (op))
- return false;
-
- rtx element = CONST_VECTOR_ELT (op, 0);
- if (!CONST_INT_P (element) && !CONST_DOUBLE_P (element))
- return false;
-
- for (size_t i = 1; i < GET_MODE_NUNITS (mode); i++)
- if (!rtx_equal_p (element, CONST_VECTOR_ELT (op, i)))
- return false;
-
- return true;
-}
-
-/* Return true if OP is of the given MODE and can be synthesized with ISA 3.1
- XXSPLTIW instruction.
-
- Return the constant via CONSTANT_PTR to use in the XXSPLTIW instruction.
- The assembler does not like negative numbers for XXSPLTIW, so we need to
- return a 16-bit unsigned value. */
-
-bool
-xxspltiw_constant_p (rtx op,
- machine_mode mode,
- HOST_WIDE_INT *constant_ptr)
-{
- HOST_WIDE_INT value;
-
- *constant_ptr = 0;
-
- if (!TARGET_PREFIXED || !TARGET_VSX || !TARGET_XXSPLTIW)
- return false;
-
- if (!CONST_VECTOR_P (op))
- return true;
-
- rtx element0 = CONST_VECTOR_ELT (op, 0);
-
- switch (mode)
- {
- /* V4SImode constant vectors that have the same element are can be used
- with XXSPLTIW. */
- case V4SImode:
- if (!const_vector_all_elements_equal_p (op, mode))
- return false;
-
- /* Don't return true if we can use the shorter vspltisw instruction. */
- value = INTVAL (element0);
- if (EASY_VECTOR_15 (value))
- return false;
-
- *constant_ptr = value & 0xffffffff;
- return true;
-
- /* V4SFmode constant vectors that have the same element are
- can be used with XXSPLTIW. */
- case V4SFmode:
- if (!const_vector_all_elements_equal_p (op, mode))
- return false;
-
- /* Don't return true for 0.0f, since that can be created with
- xxspltib or xxlxor. */
- if (element0 == CONST0_RTX (SFmode))
- return false;
-
- value = rs6000_const_f32_to_i32 (element0);
- *constant_ptr = value & 0xffffffff;
- return true;
-
- /* V8Hmode constant vectors that have the same element are can be used
- with XXSPLTIW. */
- case V8HImode:
- if (const_vector_all_elements_equal_p (op, mode))
- {
- /* Don't return true if we can use the shorter vspltish instruction. */
- value = INTVAL (element0);
- if (EASY_VECTOR_15 (value))
- return false;
-
- value &= 0xffff;
- *constant_ptr = (value << 16) | value;
- return true;
- }
-
- else
- {
- /* Check if all even elements are the same and all odd elements are
- the same. */
- rtx element1 = CONST_VECTOR_ELT (op, 1);
-
- if (!CONST_INT_P (element1))
- return false;
-
- for (size_t i = 2; i < GET_MODE_NUNITS (V8HImode); i += 2)
- if (!rtx_equal_p (element0, CONST_VECTOR_ELT (op, i))
- || !rtx_equal_p (element1, CONST_VECTOR_ELT (op, i + 1)))
- return false;
-
- HOST_WIDE_INT value0 = INTVAL (element0) & 0xffff;
- HOST_WIDE_INT value1 = INTVAL (element1) & 0xffff;
-
- if (!BYTES_BIG_ENDIAN)
- std::swap (value0, value1);
-
- *constant_ptr = (value0 << 16) | value1;
- return true;
- }
-
- /* V16QI constant vectors that have the first four elements identical to
- the next set of 4 elements, and so forth can generate XXSPLTIW. */
- case V16QImode:
- {
- if (xxspltib_constant_nosplit (op, mode))
- return false;
-
- rtx element1 = CONST_VECTOR_ELT (op, 1);
- rtx element2 = CONST_VECTOR_ELT (op, 2);
- rtx element3 = CONST_VECTOR_ELT (op, 3);
-
- if (!CONST_INT_P (element0) || !CONST_INT_P (element1)
- || !CONST_INT_P (element2) || !CONST_INT_P (element3))
- return false;
-
- for (size_t i = 4; i < GET_MODE_NUNITS (V16QImode); i += 4)
- if (!rtx_equal_p (element0, CONST_VECTOR_ELT (op, i))
- || !rtx_equal_p (element1, CONST_VECTOR_ELT (op, i + 1))
- || !rtx_equal_p (element2, CONST_VECTOR_ELT (op, i + 2))
- || !rtx_equal_p (element3, CONST_VECTOR_ELT (op, i + 3)))
- return false;
-
- HOST_WIDE_INT value0 = INTVAL (element0) & 0xff;
- HOST_WIDE_INT value1 = INTVAL (element1) & 0xff;
- HOST_WIDE_INT value2 = INTVAL (element2) & 0xff;
- HOST_WIDE_INT value3 = INTVAL (element3) & 0xff;
-
- if (BYTES_BIG_ENDIAN)
- *constant_ptr = ((value0 << 24) | (value1 << 16) | (value2 << 8)
- | value3);
- else
- *constant_ptr = ((value3 << 24) | (value2 << 16) | (value1 << 8)
- | value0);
-
- return true;
- }
-
- default:
- break;
- }
-
- return false;
-}
-
/* Return true if OP is of the given MODE and can be synthesized with ISA 3.1
XXSPLTIDP instruction.
@@ -6926,119 +6764,6 @@ lxvkq_constant_p (rtx op,
return false;
}
-/* Return true if OP is a floating point constant that can be loaded with the
- XXSPLTI32DX instruction. If the constant can be loaded with the simpler
- XXSPLTIDP (constants that can fit as SFmode constants) or XXSPLTIB (0.0)
- instructions, return false.
-
- Return the two 32-bit constants to use in the two XXSPLTI32DX instructions
- via HIGH_PTR and LOW_PTR. */
-
-static bool
-xxsplti32dx_constant_float_p (rtx op,
- machine_mode mode,
- HOST_WIDE_INT *high_ptr,
- HOST_WIDE_INT *low_ptr)
-{
- HOST_WIDE_INT xxspltidp_value = 0;
-
- if (!CONST_DOUBLE_P (op))
- return false;
-
- if (mode != SFmode && mode != DFmode)
- return false;
-
- if (op == CONST0_RTX (mode))
- return false;
-
- if (xxspltidp_constant_p (op, mode, &xxspltidp_value))
- return false;
-
- long high_low[2];
- const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (op);
- REAL_VALUE_TO_TARGET_DOUBLE (*rv, high_low);
-
- /* The double precision value is laid out in memory order. We need to undo
- this for XXSPLTI32DX. */
- if (!BYTES_BIG_ENDIAN)
- std::swap (high_low[0], high_low[1]);
-
- *high_ptr = high_low[0];
- *low_ptr = high_low[1];
- return true;
-}
-
-/* Return true if OP is of the given MODE and can be synthesized with ISA 3.1
- XXSPLTI32DX instruction. If the instruction can be synthesized with
- XXSPLTIDP or is 0/-1, return false.
-
- We handle the following types of constants:
-
- 1) vector double constants where each element is the same and you can't
- load the constant with XXSPLTIDP;
-
- 2) vector long long constants where each element is the same;
-
- 3) Scalar floating point constants that can't be loaded with XXSPLTIDP.
-
- Return the two 32-bit constants to use in the two XXSPLTI32DX instructions
- via HIGH_PTR and LOW_PTR. */
-
-bool
-xxsplti32dx_constant_p (rtx op,
- machine_mode mode,
- HOST_WIDE_INT *high_ptr,
- HOST_WIDE_INT *low_ptr)
-{
- *high_ptr = *low_ptr = 0;
-
- if (!TARGET_PREFIXED || !TARGET_VSX || !TARGET_XXSPLTI32DX)
- return false;
-
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- if (op == CONST0_RTX (mode))
- return false;
-
- switch (mode)
- {
- default:
- break;
-
- case E_V2DFmode:
- {
- if (!const_vector_all_elements_equal_p (op, mode))
- return false;
-
- rtx ele = CONST_VECTOR_ELT (op, 0);
- return xxsplti32dx_constant_float_p (ele, DFmode, high_ptr, low_ptr);
- }
-
- case E_SFmode:
- case E_DFmode:
- return xxsplti32dx_constant_float_p (op, mode, high_ptr, low_ptr);
-
- case E_V2DImode:
- {
- if (!const_vector_all_elements_equal_p (op, mode))
- return false;
-
- /* If we can generate XXSPLTIB and VEXTSB2D, don't return true. */
- rtx ele = CONST_VECTOR_ELT (op, 0);
- HOST_WIDE_INT value = INTVAL (ele);
- if (IN_RANGE (value, -128, 127))
- return false;
-
- *high_ptr = (value >> 32) & 0xffffffff;
- *low_ptr = value & 0xffffffff;
- return true;
- }
- }
-
- return false;
-}
-
const char *
output_vec_const_move (rtx *operands)
{
@@ -7054,7 +6779,6 @@ output_vec_const_move (rtx *operands)
{
bool dest_vmx_p = ALTIVEC_REGNO_P (REGNO (dest));
int xxspltib_value = 256;
- HOST_WIDE_INT xxspltiw_value = 0;
HOST_WIDE_INT xxspltidp_value = 0;
int num_insns = -1;
int lxvkq_immediate = 0;
@@ -7086,12 +6810,6 @@ output_vec_const_move (rtx *operands)
gcc_unreachable ();
}
- if (xxspltiw_constant_p (vec, mode, &xxspltiw_value))
- {
- operands[2] = GEN_INT (xxspltiw_value);
- return "xxspltiw %x0,%2";
- }
-
if (xxspltidp_constant_p (vec, mode, &xxspltidp_value))
{
operands[2] = GEN_INT (xxspltidp_value);
@@ -7104,9 +6822,6 @@ output_vec_const_move (rtx *operands)
return "lxvkq %x0,%2";
}
- if (xxsplti32dx_operand (vec, mode))
- return "#";
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
{
@@ -26878,19 +26593,10 @@ prefixed_permute_p (rtx_insn *insn)
switch (mode)
{
- case V8HImode:
- case V4SImode:
- case V4SFmode:
- return xxspltiw_operand (src, mode);
-
case DFmode:
case SFmode:
case V2DFmode:
- return (xxspltidp_operand (src, mode)
- || xxsplti32dx_operand (src, mode));
-
- case V2DImode:
- return xxsplti32dx_operand (src, mode);
+ return xxspltidp_operand (src, mode);
default:
break;
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index d6af66a1728..bf3bfed3b88 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -7728,17 +7728,17 @@
;;
;; LWZ LFS LXSSP LXSSPX STFS STXSSP
;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP
-;; MR MT<x> MF<x> NOP XXSPLTIDP XXSPLTI32DX
+;; MR MT<x> MF<x> NOP XXSPLTIDP
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, wY,
Z, m, wa, !r, f, wa,
- !r, *c*l, !r, *h, wa, wa")
+ !r, *c*l, !r, *h, wa")
(match_operand:SF 1 "input_operand"
"m, m, wY, Z, f, v,
wa, r, j, j, f, wa,
- r, r, *h, 0, eF, eD"))]
+ r, r, *h, 0, eF"))]
"(register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))
&& TARGET_HARD_FLOAT
@@ -7761,24 +7761,15 @@
mt%0 %1
mf%1 %0
nop
- #
#"
[(set_attr "type"
"load, fpload, fpload, fpload, fpstore, fpstore,
fpstore, store, veclogical, integer, fpsimple, fpsimple,
- *, mtjmpr, mfjmpr, *, vecperm, vecperm")
+ *, mtjmpr, mfjmpr, *, vecperm")
(set_attr "isa"
"*, *, p9v, p8v, *, p9v,
p8v, *, *, *, *, *,
- *, *, *, *, p10, p10")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *, *,
- *, *, *, *, *, *,
- *, *, *, *, *, 2")
- (set_attr "num_insns"
- "*, *, *, *, *, *,
- *, *, *, *, *, *,
- *, *, *, *, *, 2")])
+ *, *, *, *, p10")])
;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ
;; FMR MR MT%0 MF%1 NOP
@@ -8038,18 +8029,18 @@
;; STFD LFD FMR LXSD STXSD
;; LXSD STXSD XXLOR XXLXOR GPR<-0
-;; LWZ STW MR XXSPLTIDP XXSPLTI32DX
+;; LWZ STW MR XXSPLTIDP
(define_insn "*mov<mode>_hardfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
- Y, r, !r, wa, wa")
+ Y, r, !r, wa")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
- r, Y, r, eF, eD"))]
+ r, Y, r, eF"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8067,29 +8058,20 @@
#
#
#
- #
#"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, two,
- store, load, two, vecperm, vecperm")
+ store, load, two, vecperm")
(set_attr "size" "64")
(set_attr "length"
"*, *, *, *, *,
*, *, *, *, 8,
- 8, 8, 8, *, *")
+ 8, 8, 8, *")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
- *, *, *, p10, p10")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, 2")
- (set_attr "num_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, 2")])
+ *, *, *, p10")])
;; STW LWZ MR G-const H-const F-const
@@ -8116,19 +8098,19 @@
;; STFD LFD FMR LXSD STXSD
;; LXSDX STXSDX XXLOR XXLXOR LI 0
;; STD LD MR MT{CTR,LR} MF{CTR,LR}
-;; NOP MFVSRD MTVSRD XXSPLTIDP XXSPLTI32DX
+;; NOP MFVSRD MTVSRD XXSPLTIDP
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
YZ, r, !r, *c*l, !r,
- *h, r, <f64_dm>, wa, wa")
+ *h, r, <f64_dm>, wa")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
r, YZ, r, r, *h,
- 0, <f64_dm>, r, eF, eD"))]
+ 0, <f64_dm>, r, eF"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8151,29 +8133,18 @@
nop
mfvsrd %0,%x1
mtvsrd %x0,%1
- #
#"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, integer,
store, load, *, mtjmpr, mfjmpr,
- *, mfvsr, mtvsr, vecperm, vecperm")
+ *, mfvsr, mtvsr, vecperm")
(set_attr "size" "64")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
*, *, *, *, *,
- *, p8v, p8v, p10, p10")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, 2")
- (set_attr "num_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, *")])
+ *, p8v, p8v, p10")])
;; STD LD MR MT<SPR> MF<SPR> G-const
;; H-const F-const Special
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 77ece90c710..377dadfa05c 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -648,16 +648,6 @@ mxxspltidp
Target Undocumented Var(TARGET_XXSPLTIDP) Init(1) Save
Generate (do not generate) XXSPLTIDP instructions.
-; Do not enable this by default at the present time.
-mxxspltiw
-Target Undocumented Var(TARGET_XXSPLTIW) Init(0) Save
-Generate (do not generate) XXSPLTIW instructions.
-
-; Do not enable this by default at the present time.
-mxxsplti32dx
-Target Undocumented Var(TARGET_XXSPLTI32DX) Init(0) Save
-Generate (do not generate) XXSPLTI32DX instructions.
-
; Do not enable this by default at the present time.
mlxvkq
Target Undocumented Var(TARGET_LXVKQ) Init(0) Save
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 9a99ea9331c..00f6d0eda14 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -376,7 +376,6 @@
UNSPEC_XXSPLTIW
UNSPEC_XXSPLTIDP
UNSPEC_XXSPLTI32DX
- UNSPEC_XXSPLTI32DX_CONST
UNSPEC_XXBLEND
UNSPEC_XXPERMX
])
@@ -1192,19 +1191,19 @@
;; instruction). But generate XXLXOR/XXLORC if it will avoid a register move.
;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR)
-;; XXSPLTIDP LXVKQ XXSPLTIW
+;; XXSPLTIDP LXVKQ
;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW
;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX)
(define_insn "vsx_mov<mode>_64bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, r, we, ?wQ,
- wa, wa, wa,
+ wa, wa,
?&r, ??r, ??Y, <??r>, wa, v,
?wa, v, <??r>, wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, we, r, r,
- eF, eQ, eW,
+ eF, eQ,
wQ, Y, r, r, wE, jwM,
?jwM, W, <nW>, v, wZ"))]
@@ -1216,44 +1215,44 @@
}
[(set_attr "type"
"vecstore, vecload, vecsimple, mtvsr, mfvsr, load,
- vecperm, vecperm, vecperm,
+ vecperm, vecperm,
store, load, store, *, vecsimple, vecsimple,
vecsimple, *, *, vecstore, vecload")
(set_attr "num_insns"
"*, *, *, 2, *, 2,
- *, *, *,
+ *, *,
2, 2, 2, 2, *, *,
*, 5, 2, *, *")
(set_attr "max_prefixed_insns"
"*, *, *, *, *, 2,
- *, *, *,
+ *, *,
2, 2, 2, 2, *, *,
*, *, *, *, *")
(set_attr "length"
"*, *, *, 8, *, 8,
- *, *, *,
+ *, *,
8, 8, 8, 8, *, *,
*, 20, 8, *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
- p10, p10, p10,
+ p10, p10,
*, *, *, *, p9v, *,
<VSisa>, *, *, *, *")])
;; VSX store VSX load VSX move GPR load GPR store GPR move
-;; XXSPLTIDP LXVKQ XXSPLTIW
+;; XXSPLTIDP LXVKQ
;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const
;; LVX (VMX) STVX (VMX)
(define_insn "*vsx_mov<mode>_32bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, ??r, ??Y, <??r>,
- wa, wa, wa,
+ wa, wa,
wa, v, ?wa, v, <??r>,
wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, Y, r, r,
- eF, eQ, eW,
+ eF, eQ,
wE, jwM, ?jwM, W, <nW>,
v, wZ"))]
@@ -1265,17 +1264,17 @@
}
[(set_attr "type"
"vecstore, vecload, vecsimple, load, store, *,
- vecperm, vecperm, vecperm,
+ vecperm, vecperm,
vecsimple, vecsimple, vecsimple, *, *,
vecstore, vecload")
(set_attr "length"
"*, *, *, 16, 16, 16,
- *, *, *,
+ *, *,
*, *, *, 20, 16,
*, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
- p10, p10, p10,
+ p10, p10,
p9v, *, <VSisa>, *, *,
*, *")])
@@ -4667,52 +4666,6 @@
(set_attr "length" "*,8,*")
(set_attr "isa" "*,p8v,*")])
-;; V8HI/V4SI/V4SF splat immediate constant with XXSPLTIW. We don't need to add
-;; V16QI since the xxspltib instruction already handles this case.
-(define_insn "*vsx_splat_v8hi_xxspltiw"
- [(set (match_operand:V8HI 0 "vsx_register_operand" "=wa")
- (vec_duplicate:V8HI (match_operand 1 "const_int_operand" "n")))]
- "TARGET_PREFIXED && TARGET_VSX && TARGET_XXSPLTIW
- && !s5bit_cint_operand (operands[1], VOIDmode)"
-{
- HOST_WIDE_INT value = INTVAL (operands[1]) & 0xffff;
-
- operands[2] = GEN_INT ((value << 16) | value);
- return "xxspltiw %x0,%2";
-}
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-(define_insn "*vsx_splat_v4si_xxspltiw"
- [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa")
- (vec_duplicate:V4SI (match_operand 1 "const_int_operand" "n")))]
- "TARGET_PREFIXED && TARGET_VSX && TARGET_XXSPLTIW
- && !s5bit_cint_operand (operands[1], VOIDmode)"
-{
- /* The assembler doesn't like negative numbers. */
- operands[2] = GEN_INT (INTVAL (operands[1]) & 0xffffffff);
- return "xxspltiw %x0,%2";
-}
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-(define_insn "*vsx_splat_v4sf_xxspltiw"
- [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa")
- (vec_duplicate:V4SF
- (match_operand 1 "const_double_operand" "j,F")))]
- "TARGET_PREFIXED && TARGET_VSX && TARGET_XXSPLTIW"
-{
- if (operands[1] == CONST0_RTX (V4SFmode))
- return "xxlxor %x0,%x0,%x0";
-
- /* The assembler doesn't like negative numbers. */
- long value = rs6000_const_f32_to_i32 (operands[1]);
- operands[2] = GEN_INT (value & 0xffffffff);
- return "xxspltiw %x0,%2";
-}
- [(set_attr "type" "vecsimple,vecperm")
- (set_attr "prefixed" "*,yes")])
-
;; V4SF/V4SI splat from a vector element
(define_insn "vsx_xxspltw_<mode>"
[(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa")
@@ -6621,79 +6574,6 @@
[(set_attr "type" "vecperm")
(set_attr "prefixed" "yes")])
-;; XXSPLTI32DX used to create 64-bit constants or vector constants where the
-;; even elements match and the odd elements match.
-(define_mode_iterator XXSPLTI32DX [SF DF V2DF V2DI])
-
-(define_insn_and_split "*xxsplti32dx_<mode>"
- [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa")
- (match_operand:XXSPLTI32DX 1 "xxsplti32dx_operand" "eD"))]
- "TARGET_XXSPLTI32DX"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (unspec:XXSPLTI32DX [(match_dup 2)
- (match_dup 3)] UNSPEC_XXSPLTI32DX_CONST))
- (set (match_dup 0)
- (unspec:XXSPLTI32DX [(match_dup 0)
- (match_dup 4)
- (match_dup 5)] UNSPEC_XXSPLTI32DX_CONST))]
-{
- HOST_WIDE_INT high = 0, low = 0;
-
- if (!xxsplti32dx_constant_p (operands[1], <MODE>mode, &high, &low))
- gcc_unreachable ();
-
- /* If the low bits are 0 or all 1s, initialize that word first. This way we
- can use a smaller XXSPLTIB/XXLXOR/XXLORC instruction instead the first
- XXSPLTI32DX. */
- if (low == 0 || low == -1)
- {
- operands[2] = const1_rtx;
- operands[3] = GEN_INT (low);
- operands[4] = const0_rtx;
- operands[5] = GEN_INT (high);
- }
- else
- {
- operands[2] = const0_rtx;
- operands[3] = GEN_INT (high);
- operands[4] = const1_rtx;
- operands[5] = GEN_INT (low);
- }
-}
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")
- (set_attr "num_insns" "2")
- (set_attr "max_prefixed_insns" "2")])
-
-;; First word of XXSPLTI32DX
-(define_insn "*xxsplti32dx_<mode>_first"
- [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa,wa,wa")
- (unspec:XXSPLTI32DX [(match_operand 1 "u1bit_cint_operand" "n,n,n")
- (match_operand 2 "const_int_operand" "O,wM,n")]
- UNSPEC_XXSPLTI32DX_CONST))]
- "TARGET_XXSPLTI32DX"
- "@
- xxlxor %x0,%x0,%x0
- xxlorc %x0,%x0,%x0
- xxsplti32dx %x0,%1,%2"
- [(set_attr "type" "veclogical,veclogical,vecperm")
- (set_attr "prefixed" "*,*,yes")])
-
-;; Second word of XXSPLTI32DX
-(define_insn "*xxsplti32dx_<mode>_second"
- [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa")
- (unspec:XXSPLTI32DX [(match_operand:XXSPLTI32DX 1 "vsx_register_operand" "0")
- (match_operand 2 "u1bit_cint_operand" "n")
- (match_operand 3 "const_int_operand" "n")]
- UNSPEC_XXSPLTI32DX_CONST))]
- "TARGET_XXSPLTI32DX"
- "xxsplti32dx %x0,%2,%3"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-
;; XXBLEND built-in function support
(define_insn "xxblend_<mode>"
[(set (match_operand:VM3 0 "register_operand" "=wa")
diff --git a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
index 7fb6ec978a6..bd1502bb30a 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
@@ -26,10 +26,9 @@ vector signed long long splats4(void)
/* Codegen will consist of splat and shift instructions for most types.
If folding is enabled, the vec_sl tests using vector long long type will
- generate a lvx instead of a vspltisw+vsld pair. On power10, it may
- generate an xxsplti32dx instead of a load. */
+ generate a lvx instead of a vspltisw+vsld pair. */
/* { dg-final { scan-assembler-times {\mvspltis[bhw]\M} 0 } } */
/* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 0 } } */
-/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M|\mxxsplti32dx\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
index daa9b584845..8f6e176f9af 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -mxxsplti32dx -O2" } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
#include <math.h>
@@ -48,16 +48,13 @@ scalar_double_m_inf (void) /* XXSPLTIDP. */
double
scalar_double_pi (void)
{
- return M_PI; /* 2x XXSPLTI32DX. */
+ return M_PI; /* PLFD. */
}
double
scalar_double_denorm (void)
{
- return 0x1p-149f; /* XXLXOR, XXSPLTI32DX. */
+ return 0x1p-149f; /* PLFD. */
}
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
-/* { dg-final { scan-assembler-not {\mplfd\M} } } */
-/* { dg-final { scan-assembler-not {\mplxsd\M} } } */
+/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
index 74b2466f74c..72504bdfbbd 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -mxxsplti32dx -O2" } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
#include <math.h>
@@ -57,7 +57,4 @@ scalar_float_denorm (void)
return 0x1p-149f; /* PLFS. */
}
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mplfs\M} } } */
-/* { dg-final { scan-assembler-not {\mplxssp\M} } } */
+/* { dg-final { scan-assembler-times {\mxxspltidp\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
deleted file mode 100644
index 2707d86e6fd..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V16HI vector constants where the
- first 4 elements are the same as the next 4 elements, etc. */
-
-vector unsigned char
-v16qi_const_1 (void)
-{
- return (vector unsigned char) { 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, }; /* VSLTPISB. */
-}
-
-vector unsigned char
-v16qi_const_2 (void)
-{
- return (vector unsigned char) { 1, 2, 3, 4, 1, 2, 3, 4,
- 1, 2, 3, 4, 1, 2, 3, 4, }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvspltisb\M|\mxxspltib\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
index f438c3787a0..82ffc86f8aa 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -mxxsplti32dx -O2" } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
#include <math.h>
@@ -51,16 +51,14 @@ v2df_double_m_inf (void)
vector double
v2df_double_pi (void)
{
- return (vector double) { M_PI, M_PI }; /* 2x XXSPLTI32DX. */
+ return (vector double) { M_PI, M_PI }; /* PLVX. */
}
vector double
v2df_double_denorm (void)
{
return (vector double) { (double)0x1p-149f,
- (double)0x1p-149f }; /* XXLXOR, XXSPLTI32DX. */
+ (double)0x1p-149f }; /* PLVX. */
}
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
+/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
deleted file mode 100644
index 05d4ee3f5cb..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SF vector constants. */
-
-vector float
-v4sf_const_1 (void)
-{
- return (vector float) { 1.0f, 1.0f, 1.0f, 1.0f }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_nan (void)
-{
- return (vector float) { __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf ("") }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_inf (void)
-{
- return (vector float) { __builtin_inff (),
- __builtin_inff (),
- __builtin_inff (),
- __builtin_inff () }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_m0 (void)
-{
- return (vector float) { -0.0f, -0.0f, -0.0f, -0.0f }; /* XXSPLTIB/VSLW. */
-}
-
-vector float
-v4sf_splats_1 (void)
-{
- return vec_splats (1.0f); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_nan (void)
-{
- return vec_splats (__builtin_nanf ("")); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_inf (void)
-{
- return vec_splats (__builtin_inff ()); /* XXSPLTIW. */
-}
-
-vector float
-v8hi_splats_m0 (void)
-{
- return vec_splats (-0.0f); /* XXSPLTIB/VSLW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvslw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
deleted file mode 100644
index da909e948b2..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SI vector constants. We make sure
- the power9 support (XXSPLTIB/VEXTSB2W) is not done. */
-
-vector int
-v4si_const_1 (void)
-{
- return (vector int) { 1, 1, 1, 1 }; /* VSLTPISW. */
-}
-
-vector int
-v4si_const_126 (void)
-{
- return (vector int) { 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_const_1023 (void)
-{
- return (vector int) { 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_splats_1 (void)
-{
- return vec_splats (1); /* VSLTPISW. */
-}
-
-vector int
-v4si_splats_126 (void)
-{
- return vec_splats (126); /* XXSPLTIW. */
-}
-
-vector int
-v8hi_splats_1023 (void)
-{
- return vec_splats (1023); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mvspltisw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvextsb2w\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
deleted file mode 100644
index 290e05d4a64..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V8HI vector constants. We make sure
- the power9 support (XXSPLTIB/VUPKLSB) is not done. */
-
-vector short
-v8hi_const_1 (void)
-{
- return (vector short) { 1, 1, 1, 1, 1, 1, 1, 1 }; /* VSLTPISH. */
-}
-
-vector short
-v8hi_const_126 (void)
-{
- return (vector short) { 126, 126, 126, 126,
- 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_const_1023 (void)
-{
- return (vector short) { 1023, 1023, 1023, 1023,
- 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1 (void)
-{
- return vec_splats ((short)1); /* VSLTPISH. */
-}
-
-vector short
-v8hi_splats_126 (void)
-{
- return vec_splats ((short)126); /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1023 (void)
-{
- return vec_splats ((short)1023); /* XXSPLTIW. */
-}
-
-/* Test that we can optimiza V8HI where all of the even elements are the same
- and all of the odd elements are the same. */
-vector short
-v8hi_const_1023_1000 (void)
-{
- return (vector short) { 1023, 1000, 1023, 1000,
- 1023, 1000, 1023, 1000 }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mvspltish\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvupklsb\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
index 6ed60dfcb98..a135279b1d7 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
@@ -149,6 +149,8 @@ main (int argc, char *argv [])
return 0;
}
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mxxspltiw\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
+
+
^ permalink raw reply [flat|nested] 4+ messages in thread
* [gcc(refs/users/meissner/heads/work067)] Revert patches.
@ 2021-09-06 23:49 Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2021-09-06 23:49 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:f51d2dbc15fb9a5d6fd702c03b8e03b7f6c662aa
commit f51d2dbc15fb9a5d6fd702c03b8e03b7f6c662aa
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Sep 6 19:46:42 2021 -0400
Revert patches.
2021-09-02 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patch.
* config/rs6000/constraint.md (eD): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): If the constant
can be loaded with XXSPLTI32DX, it is easy.
(xxsplti32dx_operand): New predicate.
(easy_vector_constant): If the constant can be loaded with
XXSPLTI32DX, it is easy.
* config/rs6000/rs6000-protos.h (xxsplti32dx_constant_p): New
declaration.
* config/rs6000/rs6000.c (xxsplti32dx_constant_float_p): New
helper function.
(xxsplti32dx_constant_p): New function.
(output_vec_const_move): If the operand can be loaded with
XXSPLTI32DX, split it.
(prefixed_permute_p): Constants loaded with XXSPLTI32DX are
prefixed.
* config/rs6000/rs6000.md (movsf_hardfloat): Add support for
constants loaded with XXSPLTI32DX.
(mov<mode>_hardfloat32, FMOVE64 iterator): Add support for
constants loaded with XXSPLTI32DX.
(mov<mode>_hardfloat64, FMOVE64 iterator): Add support for
constants loaded with XXSPLTI32DX.
* config/rs6000/rs6000.opt (-mxxsplti32dx): New option.
* config/rs6000/vsx.md (UNSPEC_XXSPLTI32DX_CONST): New unspec.
(XXSPLTI32DX): New mode iterator.
(xxsplti32dx_<mode>): New insn and splitter for XXSPLTI32DX.
(xxsplti32dx_<mode>_first): New insn.
(xxsplti32dx_<mode>_second): New insn.
gcc/testsuite/
Revert patch.
* gcc.target/powerpc/pr86731-fwrapv-longlong.c: Update insn
count.
* gcc.target/powerpc/vec-splat-constant-sf.c: Update insn count.
Add -mxxsplti32dx option.
* gcc.target/powerpc/vec-splat-constant-df.c: Likewise.
* gcc.target/powerpc/vec-splat-constant-v2df.c: Likewise.
gcc/
Revert patch.
* config/rs6000/constraints.md (eW): New constraint.
* config/rs6000/predicates.md (xxspltiw_operand): New predicate.
(easy_vector_constant): If we can use XXSPLTIW, the vector
constant is easy.
* config/rs6000/rs6000-protos.h (xxspltiw_constant_p): New
declaration.
* config/rs6000/rs6000.c (xxspltib_constant_p): If we can generate
XXSPLTIW, don't generate a XXSPLTIB and an extend instruction.
(const_vector_all_elements_equal_p): New function.
(xxspltiw_constant_p): New function.
(output_vec_const_move): Add support for loading up vector
constants with XXSPLTIW.
(prefixed_permute_p): Recognize xxspltiw instructions as
prefixed.
* config/rs6000/rs6000.opt (-mxxspltiw): New debug switch.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
constants loaded with XXSPLTIW.
(vsx_mov<mode>_32bit): Likewise.
(vsx_splat_v8hi_xxspltiw): New insn.
(vsx_splat_v4si_xxspltiw): New insn.
(vsx_splat_v4sf_xxspltiw): New insn.
gcc/testsuite/
Revert patch.
* gcc.target/powerpc/vec-splat-constant-v16qi.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4si.c: New test.
* gcc.target/powerpc/vec-splat-constant-v8hi.c: New test.
* gcc.target/powerpc/vec-splati-runnable.c: Update insn counts.
gcc/
Revert patch.
* config/rs6000/constraints.md (eQ): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): If we can use
LXVKQ, it is an easy floating point constant.
(lxvkq_operand): New predicate.
* config/rs6000/rs6000-protos.h (lxvkq_constant_p): New
declaration.
* config/rs6000/rs6000.c (lxvkq_constant_p): New function.
(output_vec_const_move): Add support for LXVKQ.
(rs6000_output_move_128bit): Likewise.
* config/rs6000/rs6000.opt (-mlxvkq): New debug option.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
LXVKQ.
(vsx_mov<mode>_32bit): Likewise.
gcc/testsuite/
Revert patch.
* gcc.target/powerpc/float128-constant.c: New test.
Diff:
---
gcc/config/rs6000/constraints.md | 16 -
gcc/config/rs6000/predicates.md | 46 ---
gcc/config/rs6000/rs6000-protos.h | 4 -
gcc/config/rs6000/rs6000.c | 418 +--------------------
gcc/config/rs6000/rs6000.md | 61 +--
gcc/config/rs6000/rs6000.opt | 15 -
gcc/config/rs6000/vsx.md | 148 +-------
.../gcc.target/powerpc/float128-constant.c | 144 -------
.../gcc.target/powerpc/pr86731-fwrapv-longlong.c | 5 +-
.../gcc.target/powerpc/vec-splat-constant-df.c | 11 +-
.../gcc.target/powerpc/vec-splat-constant-sf.c | 7 +-
.../gcc.target/powerpc/vec-splat-constant-v16qi.c | 27 --
.../gcc.target/powerpc/vec-splat-constant-v2df.c | 10 +-
.../gcc.target/powerpc/vec-splat-constant-v4sf.c | 67 ----
.../gcc.target/powerpc/vec-splat-constant-v4si.c | 51 ---
.../gcc.target/powerpc/vec-splat-constant-v8hi.c | 62 ---
.../gcc.target/powerpc/vec-splati-runnable.c | 4 +-
17 files changed, 46 insertions(+), 1050 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 6317f928dc4..ea2e4a267c3 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -208,12 +208,6 @@
(and (match_code "const_int")
(match_test "((- (unsigned HOST_WIDE_INT) ival) + 0x8000) < 0x10000")))
-;; SF/DF/V2DF/DI/V2DI scalar or vector constant that can be loaded with a pair
-;; of XXSPLTI32DX instructions.
-(define_constraint "eD"
- "A vector constant that can be loaded with XXSPLTI32DX instructions."
- (match_operand 0 "xxsplti32dx_operand"))
-
;; SF/DF/V2DF scalar or vector constant that can be loaded with XXSPLTIDP
(define_constraint "eF"
"A vector constant that can be loaded with the XXSPLTIDP instruction."
@@ -224,16 +218,6 @@
"A signed 34-bit integer constant if prefixed instructions are supported."
(match_operand 0 "cint34_operand"))
-;; Vector constant that can be loaded with XXSPLTIW
-(define_constraint "eW"
- "A vector constant that can be loaded with the XXSPLTIW instruction."
- (match_operand 0 "xxspltiw_operand"))
-
-;; KF/TF scalar than can be loaded with LXVKQ
-(define_constraint "eQ"
- "An IEEE 128-bit constant that can be loaded with the LXVKQ instruction."
- (match_operand 0 "lxvkq_operand"))
-
;; Floating-point constraints. These two are defined so that insn
;; length attributes can be calculated exactly.
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index a5d51f4ad84..134243e404b 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -606,16 +606,6 @@
if (xxspltidp_operand (op, mode))
return 1;
- /* If we have the ISA 3.1 LXVKQ instruction, see if the constant can be loaded
- with that instruction. */
- if (lxvkq_operand (op, mode))
- return 1;
-
- /* If we have the ISA 3.1 XXSPLTI32DX instruction, see if the constant can
- be loaded with a pair of those instructions. */
- if (xxsplti32dx_operand (op, mode))
- return 1;
-
/* Otherwise consider floating point constants hard, so that the
constant gets pushed to memory during the early RTL phases. This
has the advantage that double precision constants that can be
@@ -655,16 +645,6 @@
return num_insns == 1;
})
-;; Return 1 if the operand is a CONST_VECTOR that can be loaded with the
-;; XXSPLTIW instruction.
-(define_predicate "xxspltiw_operand"
- (match_code "const_vector")
-{
- HOST_WIDE_INT xxspltiw_value = 0;
-
- return xxspltiw_constant_p (op, mode, &xxspltiw_value);
-})
-
;; Return 1 if operand is a SF/DF CONST_DOUBLE or V2DF CONST_VECTOR that can be
;; loaded via the ISA 3.1 XXSPLTIDP instruction.
(define_predicate "xxspltidp_operand"
@@ -674,26 +654,6 @@
return xxspltidp_constant_p (op, mode, &value);
})
-;; Return 1 if the operand is an IEEE 128-bit special constant that can be
-;; loaded with the LXVKQ instruction.
-(define_predicate "lxvkq_operand"
- (match_code "const_double")
-{
- int immediate = 0;
- return lxvkq_constant_p (op, mode, &immediate);
-})
-
-;; Return 1 if operand is a SF/DF CONST_DOUBLE or V2DF/V2DI CONST_VECTOR that
-;; can be loaded via a pair f ISA 3.1 XXSPLTI32DX instructions. Do not return
-;; true if the value can be loaded with the XXSPLTIDP instruction or XXSPLTIB
-;; to load 0.
-(define_predicate "xxsplti32dx_operand"
- (match_code "const_double,const_vector,vec_duplicate")
-{
- HOST_WIDE_INT high = 0, low = 0;
- return xxsplti32dx_constant_p (op, mode, &high, &low);
-})
-
;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
;; vector register without using memory.
(define_predicate "easy_vector_constant"
@@ -707,15 +667,9 @@
if (zero_constant (op, mode) || all_ones_constant (op, mode))
return true;
- if (xxspltiw_operand (op, mode))
- return true;
-
if (xxspltidp_operand (op, mode))
return true;
- if (xxsplti32dx_operand (op, mode))
- return true;
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (op, mode, &num_insns, &value))
return true;
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 744b1ad73e6..9bba57c22f2 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -33,10 +33,6 @@ extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, int, int, int,
extern int easy_altivec_constant (rtx, machine_mode);
extern bool xxspltib_constant_p (rtx, machine_mode, int *, int *);
extern bool xxspltidp_constant_p (rtx, machine_mode, HOST_WIDE_INT *);
-extern bool xxspltiw_constant_p (rtx, machine_mode, HOST_WIDE_INT *);
-extern bool xxsplti32dx_constant_p (rtx, machine_mode, HOST_WIDE_INT *,
- HOST_WIDE_INT *);
-extern bool lxvkq_constant_p (rtx, machine_mode, int *);
extern int vspltis_shifted (rtx);
extern HOST_WIDE_INT const_vector_elt_as_int (rtx, unsigned int);
extern bool macho_lo_sum_memory_operand (rtx, machine_mode);
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 7bbf29a3e1c..64b21535464 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6583,10 +6583,6 @@ xxspltib_constant_p (rtx op,
else if (IN_RANGE (value, -1, 0))
*num_insns_ptr = 1;
- /* See if we could generate XXSPLTIW directly. */
- else if (xxspltiw_operand (op, mode))
- return false;
-
else
*num_insns_ptr = 2;
@@ -6594,164 +6590,6 @@ xxspltib_constant_p (rtx op,
return true;
}
-/* Return true if the argument is a constant vector where all elements are the
- same. */
-
-static bool
-const_vector_all_elements_equal_p (rtx op, machine_mode mode)
-{
- if (!CONST_VECTOR_P (op))
- return false;
-
- rtx element = CONST_VECTOR_ELT (op, 0);
- if (!CONST_INT_P (element) && !CONST_DOUBLE_P (element))
- return false;
-
- for (size_t i = 1; i < GET_MODE_NUNITS (mode); i++)
- if (!rtx_equal_p (element, CONST_VECTOR_ELT (op, i)))
- return false;
-
- return true;
-}
-
-/* Return true if OP is of the given MODE and can be synthesized with ISA 3.1
- XXSPLTIW instruction.
-
- Return the constant via CONSTANT_PTR to use in the XXSPLTIW instruction.
- The assembler does not like negative numbers for XXSPLTIW, so we need to
- return a 16-bit unsigned value. */
-
-bool
-xxspltiw_constant_p (rtx op,
- machine_mode mode,
- HOST_WIDE_INT *constant_ptr)
-{
- HOST_WIDE_INT value;
-
- *constant_ptr = 0;
-
- if (!TARGET_PREFIXED || !TARGET_VSX || !TARGET_XXSPLTIW)
- return false;
-
- if (!CONST_VECTOR_P (op))
- return true;
-
- rtx element0 = CONST_VECTOR_ELT (op, 0);
-
- switch (mode)
- {
- /* V4SImode constant vectors that have the same element are can be used
- with XXSPLTIW. */
- case V4SImode:
- if (!const_vector_all_elements_equal_p (op, mode))
- return false;
-
- /* Don't return true if we can use the shorter vspltisw instruction. */
- value = INTVAL (element0);
- if (EASY_VECTOR_15 (value))
- return false;
-
- *constant_ptr = value & 0xffffffff;
- return true;
-
- /* V4SFmode constant vectors that have the same element are
- can be used with XXSPLTIW. */
- case V4SFmode:
- if (!const_vector_all_elements_equal_p (op, mode))
- return false;
-
- /* Don't return true for 0.0f, since that can be created with
- xxspltib or xxlxor. */
- if (element0 == CONST0_RTX (SFmode))
- return false;
-
- value = rs6000_const_f32_to_i32 (element0);
- *constant_ptr = value & 0xffffffff;
- return true;
-
- /* V8Hmode constant vectors that have the same element are can be used
- with XXSPLTIW. */
- case V8HImode:
- if (const_vector_all_elements_equal_p (op, mode))
- {
- /* Don't return true if we can use the shorter vspltish instruction. */
- value = INTVAL (element0);
- if (EASY_VECTOR_15 (value))
- return false;
-
- value &= 0xffff;
- *constant_ptr = (value << 16) | value;
- return true;
- }
-
- else
- {
- /* Check if all even elements are the same and all odd elements are
- the same. */
- rtx element1 = CONST_VECTOR_ELT (op, 1);
-
- if (!CONST_INT_P (element1))
- return false;
-
- for (size_t i = 2; i < GET_MODE_NUNITS (V8HImode); i += 2)
- if (!rtx_equal_p (element0, CONST_VECTOR_ELT (op, i))
- || !rtx_equal_p (element1, CONST_VECTOR_ELT (op, i + 1)))
- return false;
-
- HOST_WIDE_INT value0 = INTVAL (element0) & 0xffff;
- HOST_WIDE_INT value1 = INTVAL (element1) & 0xffff;
-
- if (!BYTES_BIG_ENDIAN)
- std::swap (value0, value1);
-
- *constant_ptr = (value0 << 16) | value1;
- return true;
- }
-
- /* V16QI constant vectors that have the first four elements identical to
- the next set of 4 elements, and so forth can generate XXSPLTIW. */
- case V16QImode:
- {
- if (xxspltib_constant_nosplit (op, mode))
- return false;
-
- rtx element1 = CONST_VECTOR_ELT (op, 1);
- rtx element2 = CONST_VECTOR_ELT (op, 2);
- rtx element3 = CONST_VECTOR_ELT (op, 3);
-
- if (!CONST_INT_P (element0) || !CONST_INT_P (element1)
- || !CONST_INT_P (element2) || !CONST_INT_P (element3))
- return false;
-
- for (size_t i = 4; i < GET_MODE_NUNITS (V16QImode); i += 4)
- if (!rtx_equal_p (element0, CONST_VECTOR_ELT (op, i))
- || !rtx_equal_p (element1, CONST_VECTOR_ELT (op, i + 1))
- || !rtx_equal_p (element2, CONST_VECTOR_ELT (op, i + 2))
- || !rtx_equal_p (element3, CONST_VECTOR_ELT (op, i + 3)))
- return false;
-
- HOST_WIDE_INT value0 = INTVAL (element0) & 0xff;
- HOST_WIDE_INT value1 = INTVAL (element1) & 0xff;
- HOST_WIDE_INT value2 = INTVAL (element2) & 0xff;
- HOST_WIDE_INT value3 = INTVAL (element3) & 0xff;
-
- if (BYTES_BIG_ENDIAN)
- *constant_ptr = ((value0 << 24) | (value1 << 16) | (value2 << 8)
- | value3);
- else
- *constant_ptr = ((value3 << 24) | (value2 << 16) | (value1 << 8)
- | value0);
-
- return true;
- }
-
- default:
- break;
- }
-
- return false;
-}
-
/* Return true if OP is of the given MODE and can be synthesized with ISA 3.1
XXSPLTIDP instruction.
@@ -6820,225 +6658,6 @@ xxspltidp_constant_p (rtx op,
return true;
}
-/* Return true if OP is of the given MODE is one of the 18 special values that
- can be generated with the LXVKQ instruction.
-
- Return the constant that will go in the LXVKQ instruction. */
-
-/* LXVKQ immediates. */
-enum {
- LXVKQ_ONE = 1,
- LXVKQ_TWO = 2,
- LXVKQ_THREE = 3,
- LXVKQ_FOUR = 4,
- LXVKQ_FIVE = 5,
- LXVKQ_SIX = 6,
- LXVKQ_SEVEN = 7,
- LXVKQ_INF = 8,
- LXVKQ_NAN = 9,
- LXVKQ_NEG_ZERO = 16,
- LXVKQ_NEG_ONE = 17,
- LXVKQ_NEG_TWO = 18,
- LXVKQ_NEG_THREE = 19,
- LXVKQ_NEG_FOUR = 20,
- LXVKQ_NEG_FIVE = 21,
- LXVKQ_NEG_SIX = 22,
- LXVKQ_NEG_SEVEN = 23,
- LXVKQ_NEG_INF = 24
-};
-
-bool
-lxvkq_constant_p (rtx op,
- machine_mode mode,
- int *imm_p)
-{
- *imm_p = -1;
-
- if (!TARGET_LXVKQ || !TARGET_POWER10 || !TARGET_VSX || !TARGET_FLOAT128_HW)
- return false;
-
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- if (!FLOAT128_IEEE_P (mode))
- return false;
-
- if (!CONST_DOUBLE_P (op))
- return false;
-
- /* All of the values generated can be expressed as SFmode values, so if it
- doesn't fit in SFmode, exit. */
- const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (op);
- if (!exact_real_truncate (SFmode, rv))
- return 0;
-
- /* Special values (infinity, nan, -0.0. */
- if (real_isinf (rv))
- {
- *imm_p = real_isneg (rv) ? LXVKQ_NEG_INF : LXVKQ_INF;
- return true;
- }
-
- if (real_isnan (rv) && !real_isneg (rv))
- {
- *imm_p = LXVKQ_NAN;
- return true;
- }
-
- if (real_isnegzero (rv))
- {
- *imm_p = LXVKQ_NEG_ZERO;
- return true;
- }
-
- /* The other values are all integers 1..7, and -1..-7. */
- if (!real_isinteger (rv, mode))
- return false;
-
- HOST_WIDE_INT value = real_to_integer (rv);
- switch (value)
- {
- default:
- break;
-
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
- *imm_p = LXVKQ_ONE + (value - 1);
- return true;
-
- case -1:
- case -2:
- case -3:
- case -4:
- case -5:
- case -6:
- case -7:
- *imm_p = LXVKQ_NEG_ONE + (-value - 1);
- return true;
- }
-
- /* We can't load the value with LXVKQ. */
- return false;
-}
-
-/* Return true if OP is a floating point constant that can be loaded with the
- XXSPLTI32DX instruction. If the constant can be loaded with the simpler
- XXSPLTIDP (constants that can fit as SFmode constants) or XXSPLTIB (0.0)
- instructions, return false.
-
- Return the two 32-bit constants to use in the two XXSPLTI32DX instructions
- via HIGH_PTR and LOW_PTR. */
-
-static bool
-xxsplti32dx_constant_float_p (rtx op,
- machine_mode mode,
- HOST_WIDE_INT *high_ptr,
- HOST_WIDE_INT *low_ptr)
-{
- HOST_WIDE_INT xxspltidp_value = 0;
-
- if (!CONST_DOUBLE_P (op))
- return false;
-
- if (mode != SFmode && mode != DFmode)
- return false;
-
- if (op == CONST0_RTX (mode))
- return false;
-
- if (xxspltidp_constant_p (op, mode, &xxspltidp_value))
- return false;
-
- long high_low[2];
- const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (op);
- REAL_VALUE_TO_TARGET_DOUBLE (*rv, high_low);
-
- /* The double precision value is laid out in memory order. We need to undo
- this for XXSPLTI32DX. */
- if (!BYTES_BIG_ENDIAN)
- std::swap (high_low[0], high_low[1]);
-
- *high_ptr = high_low[0];
- *low_ptr = high_low[1];
- return true;
-}
-
-/* Return true if OP is of the given MODE and can be synthesized with ISA 3.1
- XXSPLTI32DX instruction. If the instruction can be synthesized with
- XXSPLTIDP or is 0/-1, return false.
-
- We handle the following types of constants:
-
- 1) vector double constants where each element is the same and you can't
- load the constant with XXSPLTIDP;
-
- 2) vector long long constants where each element is the same;
-
- 3) Scalar floating point constants that can't be loaded with XXSPLTIDP.
-
- Return the two 32-bit constants to use in the two XXSPLTI32DX instructions
- via HIGH_PTR and LOW_PTR. */
-
-bool
-xxsplti32dx_constant_p (rtx op,
- machine_mode mode,
- HOST_WIDE_INT *high_ptr,
- HOST_WIDE_INT *low_ptr)
-{
- *high_ptr = *low_ptr = 0;
-
- if (!TARGET_PREFIXED || !TARGET_VSX || !TARGET_XXSPLTI32DX)
- return false;
-
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- if (op == CONST0_RTX (mode))
- return false;
-
- switch (mode)
- {
- default:
- break;
-
- case E_V2DFmode:
- {
- if (!const_vector_all_elements_equal_p (op, mode))
- return false;
-
- rtx ele = CONST_VECTOR_ELT (op, 0);
- return xxsplti32dx_constant_float_p (ele, DFmode, high_ptr, low_ptr);
- }
-
- case E_SFmode:
- case E_DFmode:
- return xxsplti32dx_constant_float_p (op, mode, high_ptr, low_ptr);
-
- case E_V2DImode:
- {
- if (!const_vector_all_elements_equal_p (op, mode))
- return false;
-
- /* If we can generate XXSPLTIB and VEXTSB2D, don't return true. */
- rtx ele = CONST_VECTOR_ELT (op, 0);
- HOST_WIDE_INT value = INTVAL (ele);
- if (IN_RANGE (value, -128, 127))
- return false;
-
- *high_ptr = (value >> 32) & 0xffffffff;
- *low_ptr = value & 0xffffffff;
- return true;
- }
- }
-
- return false;
-}
-
const char *
output_vec_const_move (rtx *operands)
{
@@ -7054,10 +6673,8 @@ output_vec_const_move (rtx *operands)
{
bool dest_vmx_p = ALTIVEC_REGNO_P (REGNO (dest));
int xxspltib_value = 256;
- HOST_WIDE_INT xxspltiw_value = 0;
HOST_WIDE_INT xxspltidp_value = 0;
int num_insns = -1;
- int lxvkq_immediate = 0;
if (zero_constant (vec, mode))
{
@@ -7086,27 +6703,12 @@ output_vec_const_move (rtx *operands)
gcc_unreachable ();
}
- if (xxspltiw_constant_p (vec, mode, &xxspltiw_value))
- {
- operands[2] = GEN_INT (xxspltiw_value);
- return "xxspltiw %x0,%2";
- }
-
if (xxspltidp_constant_p (vec, mode, &xxspltidp_value))
{
operands[2] = GEN_INT (xxspltidp_value);
return "xxspltidp %x0,%2";
}
- if (lxvkq_constant_p (vec, mode, &lxvkq_immediate))
- {
- operands[2] = GEN_INT (lxvkq_immediate);
- return "lxvkq %x0,%2";
- }
-
- if (xxsplti32dx_operand (vec, mode))
- return "#";
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
{
@@ -13815,7 +13417,6 @@ rs6000_output_move_128bit (rtx operands[])
int src_regno;
bool dest_gpr_p, dest_fp_p, dest_vmx_p, dest_vsx_p;
bool src_gpr_p, src_fp_p, src_vmx_p, src_vsx_p;
- int lxvkq_immediate = 0;
if (REG_P (dest))
{
@@ -13960,14 +13561,6 @@ rs6000_output_move_128bit (rtx operands[])
}
/* Constants. */
- else if (dest_vmx_p
- && CONST_DOUBLE_P (src)
- && lxvkq_constant_p (src, mode, &lxvkq_immediate))
- {
- operands[2] = GEN_INT (lxvkq_immediate);
- return "lxvkq %x0,%2";
- }
-
else if (dest_regno >= 0
&& (CONST_INT_P (src)
|| CONST_WIDE_INT_P (src)
@@ -26878,19 +26471,10 @@ prefixed_permute_p (rtx_insn *insn)
switch (mode)
{
- case V8HImode:
- case V4SImode:
- case V4SFmode:
- return xxspltiw_operand (src, mode);
-
case DFmode:
case SFmode:
case V2DFmode:
- return (xxspltidp_operand (src, mode)
- || xxsplti32dx_operand (src, mode));
-
- case V2DImode:
- return xxsplti32dx_operand (src, mode);
+ return xxspltidp_operand (src, mode);
default:
break;
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index d6af66a1728..bf3bfed3b88 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -7728,17 +7728,17 @@
;;
;; LWZ LFS LXSSP LXSSPX STFS STXSSP
;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP
-;; MR MT<x> MF<x> NOP XXSPLTIDP XXSPLTI32DX
+;; MR MT<x> MF<x> NOP XXSPLTIDP
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, wY,
Z, m, wa, !r, f, wa,
- !r, *c*l, !r, *h, wa, wa")
+ !r, *c*l, !r, *h, wa")
(match_operand:SF 1 "input_operand"
"m, m, wY, Z, f, v,
wa, r, j, j, f, wa,
- r, r, *h, 0, eF, eD"))]
+ r, r, *h, 0, eF"))]
"(register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))
&& TARGET_HARD_FLOAT
@@ -7761,24 +7761,15 @@
mt%0 %1
mf%1 %0
nop
- #
#"
[(set_attr "type"
"load, fpload, fpload, fpload, fpstore, fpstore,
fpstore, store, veclogical, integer, fpsimple, fpsimple,
- *, mtjmpr, mfjmpr, *, vecperm, vecperm")
+ *, mtjmpr, mfjmpr, *, vecperm")
(set_attr "isa"
"*, *, p9v, p8v, *, p9v,
p8v, *, *, *, *, *,
- *, *, *, *, p10, p10")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *, *,
- *, *, *, *, *, *,
- *, *, *, *, *, 2")
- (set_attr "num_insns"
- "*, *, *, *, *, *,
- *, *, *, *, *, *,
- *, *, *, *, *, 2")])
+ *, *, *, *, p10")])
;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ
;; FMR MR MT%0 MF%1 NOP
@@ -8038,18 +8029,18 @@
;; STFD LFD FMR LXSD STXSD
;; LXSD STXSD XXLOR XXLXOR GPR<-0
-;; LWZ STW MR XXSPLTIDP XXSPLTI32DX
+;; LWZ STW MR XXSPLTIDP
(define_insn "*mov<mode>_hardfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
- Y, r, !r, wa, wa")
+ Y, r, !r, wa")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
- r, Y, r, eF, eD"))]
+ r, Y, r, eF"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8067,29 +8058,20 @@
#
#
#
- #
#"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, two,
- store, load, two, vecperm, vecperm")
+ store, load, two, vecperm")
(set_attr "size" "64")
(set_attr "length"
"*, *, *, *, *,
*, *, *, *, 8,
- 8, 8, 8, *, *")
+ 8, 8, 8, *")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
- *, *, *, p10, p10")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, 2")
- (set_attr "num_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, 2")])
+ *, *, *, p10")])
;; STW LWZ MR G-const H-const F-const
@@ -8116,19 +8098,19 @@
;; STFD LFD FMR LXSD STXSD
;; LXSDX STXSDX XXLOR XXLXOR LI 0
;; STD LD MR MT{CTR,LR} MF{CTR,LR}
-;; NOP MFVSRD MTVSRD XXSPLTIDP XXSPLTI32DX
+;; NOP MFVSRD MTVSRD XXSPLTIDP
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
YZ, r, !r, *c*l, !r,
- *h, r, <f64_dm>, wa, wa")
+ *h, r, <f64_dm>, wa")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
r, YZ, r, r, *h,
- 0, <f64_dm>, r, eF, eD"))]
+ 0, <f64_dm>, r, eF"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8151,29 +8133,18 @@
nop
mfvsrd %0,%x1
mtvsrd %x0,%1
- #
#"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, integer,
store, load, *, mtjmpr, mfjmpr,
- *, mfvsr, mtvsr, vecperm, vecperm")
+ *, mfvsr, mtvsr, vecperm")
(set_attr "size" "64")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
*, *, *, *, *,
- *, p8v, p8v, p10, p10")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, 2")
- (set_attr "num_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, *")])
+ *, p8v, p8v, p10")])
;; STD LD MR MT<SPR> MF<SPR> G-const
;; H-const F-const Special
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 77ece90c710..3e096988a73 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -647,18 +647,3 @@ Generate code that will run in privileged state.
mxxspltidp
Target Undocumented Var(TARGET_XXSPLTIDP) Init(1) Save
Generate (do not generate) XXSPLTIDP instructions.
-
-; Do not enable this by default at the present time.
-mxxspltiw
-Target Undocumented Var(TARGET_XXSPLTIW) Init(0) Save
-Generate (do not generate) XXSPLTIW instructions.
-
-; Do not enable this by default at the present time.
-mxxsplti32dx
-Target Undocumented Var(TARGET_XXSPLTI32DX) Init(0) Save
-Generate (do not generate) XXSPLTI32DX instructions.
-
-; Do not enable this by default at the present time.
-mlxvkq
-Target Undocumented Var(TARGET_LXVKQ) Init(0) Save
-Generate (do not generate) LXVKQ instructions.
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 9a99ea9331c..af9a04870d4 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -376,7 +376,6 @@
UNSPEC_XXSPLTIW
UNSPEC_XXSPLTIDP
UNSPEC_XXSPLTI32DX
- UNSPEC_XXSPLTI32DX_CONST
UNSPEC_XXBLEND
UNSPEC_XXPERMX
])
@@ -1192,19 +1191,19 @@
;; instruction). But generate XXLXOR/XXLORC if it will avoid a register move.
;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR)
-;; XXSPLTIDP LXVKQ XXSPLTIW
+;; XXSPLTIDP
;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW
;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX)
(define_insn "vsx_mov<mode>_64bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, r, we, ?wQ,
- wa, wa, wa,
+ wa,
?&r, ??r, ??Y, <??r>, wa, v,
?wa, v, <??r>, wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, we, r, r,
- eF, eQ, eW,
+ eF,
wQ, Y, r, r, wE, jwM,
?jwM, W, <nW>, v, wZ"))]
@@ -1216,44 +1215,44 @@
}
[(set_attr "type"
"vecstore, vecload, vecsimple, mtvsr, mfvsr, load,
- vecperm, vecperm, vecperm,
+ vecperm,
store, load, store, *, vecsimple, vecsimple,
vecsimple, *, *, vecstore, vecload")
(set_attr "num_insns"
"*, *, *, 2, *, 2,
- *, *, *,
+ *,
2, 2, 2, 2, *, *,
*, 5, 2, *, *")
(set_attr "max_prefixed_insns"
"*, *, *, *, *, 2,
- *, *, *,
+ *,
2, 2, 2, 2, *, *,
*, *, *, *, *")
(set_attr "length"
"*, *, *, 8, *, 8,
- *, *, *,
+ *,
8, 8, 8, 8, *, *,
*, 20, 8, *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
- p10, p10, p10,
+ p10,
*, *, *, *, p9v, *,
<VSisa>, *, *, *, *")])
;; VSX store VSX load VSX move GPR load GPR store GPR move
-;; XXSPLTIDP LXVKQ XXSPLTIW
+;; XXSPLTIDP
;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const
;; LVX (VMX) STVX (VMX)
(define_insn "*vsx_mov<mode>_32bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, ??r, ??Y, <??r>,
- wa, wa, wa,
+ wa,
wa, v, ?wa, v, <??r>,
wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, Y, r, r,
- eF, eQ, eW,
+ eF,
wE, jwM, ?jwM, W, <nW>,
v, wZ"))]
@@ -1265,17 +1264,17 @@
}
[(set_attr "type"
"vecstore, vecload, vecsimple, load, store, *,
- vecperm, vecperm, vecperm,
+ vecperm,
vecsimple, vecsimple, vecsimple, *, *,
vecstore, vecload")
(set_attr "length"
"*, *, *, 16, 16, 16,
- *, *, *,
+ *,
*, *, *, 20, 16,
*, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
- p10, p10, p10,
+ p10,
p9v, *, <VSisa>, *, *,
*, *")])
@@ -4667,52 +4666,6 @@
(set_attr "length" "*,8,*")
(set_attr "isa" "*,p8v,*")])
-;; V8HI/V4SI/V4SF splat immediate constant with XXSPLTIW. We don't need to add
-;; V16QI since the xxspltib instruction already handles this case.
-(define_insn "*vsx_splat_v8hi_xxspltiw"
- [(set (match_operand:V8HI 0 "vsx_register_operand" "=wa")
- (vec_duplicate:V8HI (match_operand 1 "const_int_operand" "n")))]
- "TARGET_PREFIXED && TARGET_VSX && TARGET_XXSPLTIW
- && !s5bit_cint_operand (operands[1], VOIDmode)"
-{
- HOST_WIDE_INT value = INTVAL (operands[1]) & 0xffff;
-
- operands[2] = GEN_INT ((value << 16) | value);
- return "xxspltiw %x0,%2";
-}
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-(define_insn "*vsx_splat_v4si_xxspltiw"
- [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa")
- (vec_duplicate:V4SI (match_operand 1 "const_int_operand" "n")))]
- "TARGET_PREFIXED && TARGET_VSX && TARGET_XXSPLTIW
- && !s5bit_cint_operand (operands[1], VOIDmode)"
-{
- /* The assembler doesn't like negative numbers. */
- operands[2] = GEN_INT (INTVAL (operands[1]) & 0xffffffff);
- return "xxspltiw %x0,%2";
-}
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-(define_insn "*vsx_splat_v4sf_xxspltiw"
- [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa")
- (vec_duplicate:V4SF
- (match_operand 1 "const_double_operand" "j,F")))]
- "TARGET_PREFIXED && TARGET_VSX && TARGET_XXSPLTIW"
-{
- if (operands[1] == CONST0_RTX (V4SFmode))
- return "xxlxor %x0,%x0,%x0";
-
- /* The assembler doesn't like negative numbers. */
- long value = rs6000_const_f32_to_i32 (operands[1]);
- operands[2] = GEN_INT (value & 0xffffffff);
- return "xxspltiw %x0,%2";
-}
- [(set_attr "type" "vecsimple,vecperm")
- (set_attr "prefixed" "*,yes")])
-
;; V4SF/V4SI splat from a vector element
(define_insn "vsx_xxspltw_<mode>"
[(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa")
@@ -6621,79 +6574,6 @@
[(set_attr "type" "vecperm")
(set_attr "prefixed" "yes")])
-;; XXSPLTI32DX used to create 64-bit constants or vector constants where the
-;; even elements match and the odd elements match.
-(define_mode_iterator XXSPLTI32DX [SF DF V2DF V2DI])
-
-(define_insn_and_split "*xxsplti32dx_<mode>"
- [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa")
- (match_operand:XXSPLTI32DX 1 "xxsplti32dx_operand" "eD"))]
- "TARGET_XXSPLTI32DX"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (unspec:XXSPLTI32DX [(match_dup 2)
- (match_dup 3)] UNSPEC_XXSPLTI32DX_CONST))
- (set (match_dup 0)
- (unspec:XXSPLTI32DX [(match_dup 0)
- (match_dup 4)
- (match_dup 5)] UNSPEC_XXSPLTI32DX_CONST))]
-{
- HOST_WIDE_INT high = 0, low = 0;
-
- if (!xxsplti32dx_constant_p (operands[1], <MODE>mode, &high, &low))
- gcc_unreachable ();
-
- /* If the low bits are 0 or all 1s, initialize that word first. This way we
- can use a smaller XXSPLTIB/XXLXOR/XXLORC instruction instead the first
- XXSPLTI32DX. */
- if (low == 0 || low == -1)
- {
- operands[2] = const1_rtx;
- operands[3] = GEN_INT (low);
- operands[4] = const0_rtx;
- operands[5] = GEN_INT (high);
- }
- else
- {
- operands[2] = const0_rtx;
- operands[3] = GEN_INT (high);
- operands[4] = const1_rtx;
- operands[5] = GEN_INT (low);
- }
-}
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")
- (set_attr "num_insns" "2")
- (set_attr "max_prefixed_insns" "2")])
-
-;; First word of XXSPLTI32DX
-(define_insn "*xxsplti32dx_<mode>_first"
- [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa,wa,wa")
- (unspec:XXSPLTI32DX [(match_operand 1 "u1bit_cint_operand" "n,n,n")
- (match_operand 2 "const_int_operand" "O,wM,n")]
- UNSPEC_XXSPLTI32DX_CONST))]
- "TARGET_XXSPLTI32DX"
- "@
- xxlxor %x0,%x0,%x0
- xxlorc %x0,%x0,%x0
- xxsplti32dx %x0,%1,%2"
- [(set_attr "type" "veclogical,veclogical,vecperm")
- (set_attr "prefixed" "*,*,yes")])
-
-;; Second word of XXSPLTI32DX
-(define_insn "*xxsplti32dx_<mode>_second"
- [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa")
- (unspec:XXSPLTI32DX [(match_operand:XXSPLTI32DX 1 "vsx_register_operand" "0")
- (match_operand 2 "u1bit_cint_operand" "n")
- (match_operand 3 "const_int_operand" "n")]
- UNSPEC_XXSPLTI32DX_CONST))]
- "TARGET_XXSPLTI32DX"
- "xxsplti32dx %x0,%2,%3"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-
;; XXBLEND built-in function support
(define_insn "xxblend_<mode>"
[(set (match_operand:VM3 0 "register_operand" "=wa")
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-constant.c b/gcc/testsuite/gcc.target/powerpc/float128-constant.c
deleted file mode 100644
index 23ee7e85d84..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/float128-constant.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/* { dg-require-effective-target ppc_float128_hw } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -mlxvkq -O2" } */
-
-/* Test whether the LXVKQ instruction is generated to load special IEEE 128-bit
- constants. */
-
-_Float128
-return_0 (void)
-{
- return 0.0f128; /* XXSPLTIB 34,0. */
-}
-
-_Float128
-return_1 (void)
-{
- return 1.0f128; /* LXVKQ 34,1. */
-}
-
-_Float128
-return_2 (void)
-{
- return 2.0f128; /* LXVKQ 34,2. */
-}
-
-_Float128
-return_3 (void)
-{
- return 3.0f128; /* LXVKQ 34,3. */
-}
-
-_Float128
-return_4 (void)
-{
- return 4.0f128; /* LXVKQ 34,4. */
-}
-
-_Float128
-return_5 (void)
-{
- return 5.0f128; /* LXVKQ 34,5. */
-}
-
-_Float128
-return_6 (void)
-{
- return 6.0f128; /* LXVKQ 34,6. */
-}
-
-_Float128
-return_7 (void)
-{
- return 7.0f128; /* LXVKQ 34,7. */
-}
-
-_Float128
-return_m0 (void)
-{
- return -0.0f128; /* LXVKQ 34,16. */
-}
-
-_Float128
-return_m1 (void)
-{
- return -1.0f128; /* LXVKQ 34,17. */
-}
-
-_Float128
-return_m2 (void)
-{
- return -2.0f128; /* LXVKQ 34,18. */
-}
-
-_Float128
-return_m3 (void)
-{
- return -3.0f128; /* LXVKQ 34,19. */
-}
-
-_Float128
-return_m4 (void)
-{
- return -4.0f128; /* LXVKQ 34,20. */
-}
-
-_Float128
-return_m5 (void)
-{
- return -5.0f128; /* LXVKQ 34,21. */
-}
-
-_Float128
-return_m6 (void)
-{
- return -6.0f128; /* LXVKQ 34,22. */
-}
-
-_Float128
-return_m7 (void)
-{
- return -7.0f128; /* LXVKQ 34,23. */
-}
-
-_Float128
-return_inf (void)
-{
- return __builtin_inff128 (); /* LXVKQ 34,8. */
-}
-
-_Float128
-return_minf (void)
-{
- return - __builtin_inff128 (); /* LXVKQ 34,24. */
-}
-
-_Float128
-return_nan (void)
-{
- return __builtin_nanf128 (""); /* LXVKQ 34,9. */
-}
-
-/* Note, the following NaNs should not generate a LXVKQ instruction. */
-_Float128
-return_mnan (void)
-{
- return - __builtin_nanf128 (""); /* PLXV 34,... */
-}
-
-_Float128
-return_nan2 (void)
-{
- return __builtin_nanf128 ("1"); /* PLXV 34,... */
-}
-
-_Float128
-return_nans (void)
-{
- return __builtin_nansf128 (""); /* PLXV 34,... */
-}
-
-/* { dg-final { scan-assembler-times {\mlxvkq\M} 18 } } */
-/* { dg-final { scan-assembler-times {\mplxv\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 1 } } */
-
diff --git a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
index 7fb6ec978a6..bd1502bb30a 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
@@ -26,10 +26,9 @@ vector signed long long splats4(void)
/* Codegen will consist of splat and shift instructions for most types.
If folding is enabled, the vec_sl tests using vector long long type will
- generate a lvx instead of a vspltisw+vsld pair. On power10, it may
- generate an xxsplti32dx instead of a load. */
+ generate a lvx instead of a vspltisw+vsld pair. */
/* { dg-final { scan-assembler-times {\mvspltis[bhw]\M} 0 } } */
/* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 0 } } */
-/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M|\mxxsplti32dx\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
index 27ded2b6d1d..8f6e176f9af 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -msplti32dx -O2" } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
#include <math.h>
@@ -48,16 +48,13 @@ scalar_double_m_inf (void) /* XXSPLTIDP. */
double
scalar_double_pi (void)
{
- return M_PI; /* 2x XXSPLTI32DX. */
+ return M_PI; /* PLFD. */
}
double
scalar_double_denorm (void)
{
- return 0x1p-149f; /* XXLXOR, XXSPLTI32DX. */
+ return 0x1p-149f; /* PLFD. */
}
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
-/* { dg-final { scan-assembler-not {\mplfd\M} } } */
-/* { dg-final { scan-assembler-not {\mplxsd\M} } } */
+/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
index 74b2466f74c..72504bdfbbd 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -mxxsplti32dx -O2" } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
#include <math.h>
@@ -57,7 +57,4 @@ scalar_float_denorm (void)
return 0x1p-149f; /* PLFS. */
}
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mplfs\M} } } */
-/* { dg-final { scan-assembler-not {\mplxssp\M} } } */
+/* { dg-final { scan-assembler-times {\mxxspltidp\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
deleted file mode 100644
index 27764ddbc83..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V16HI vector constants where the
- first 4 elements are the same as the next 4 elements, etc. */
-
-vector unsigned char
-v16qi_const_1 (void)
-{
- return (vector unsigned char) { 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, }; /* VSLTPISB. */
-}
-
-vector unsigned char
-v16qi_const_2 (void)
-{
- return (vector unsigned char) { 1, 2, 3, 4, 1, 2, 3, 4,
- 1, 2, 3, 4, 1, 2, 3, 4, }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvspltisb\M|\mxxspltib\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
index f438c3787a0..82ffc86f8aa 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -mxxsplti32dx -O2" } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
#include <math.h>
@@ -51,16 +51,14 @@ v2df_double_m_inf (void)
vector double
v2df_double_pi (void)
{
- return (vector double) { M_PI, M_PI }; /* 2x XXSPLTI32DX. */
+ return (vector double) { M_PI, M_PI }; /* PLVX. */
}
vector double
v2df_double_denorm (void)
{
return (vector double) { (double)0x1p-149f,
- (double)0x1p-149f }; /* XXLXOR, XXSPLTI32DX. */
+ (double)0x1p-149f }; /* PLVX. */
}
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
+/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
deleted file mode 100644
index 1f0475cf47a..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SF vector constants. */
-
-vector float
-v4sf_const_1 (void)
-{
- return (vector float) { 1.0f, 1.0f, 1.0f, 1.0f }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_nan (void)
-{
- return (vector float) { __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf ("") }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_inf (void)
-{
- return (vector float) { __builtin_inff (),
- __builtin_inff (),
- __builtin_inff (),
- __builtin_inff () }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_m0 (void)
-{
- return (vector float) { -0.0f, -0.0f, -0.0f, -0.0f }; /* XXSPLTIB/VSLW. */
-}
-
-vector float
-v4sf_splats_1 (void)
-{
- return vec_splats (1.0f); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_nan (void)
-{
- return vec_splats (__builtin_nanf ("")); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_inf (void)
-{
- return vec_splats (__builtin_inff ()); /* XXSPLTIW. */
-}
-
-vector float
-v8hi_splats_m0 (void)
-{
- return vec_splats (-0.0f); /* XXSPLTIB/VSLW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvslw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
deleted file mode 100644
index 02d0c6d66a2..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SI vector constants. We make sure
- the power9 support (XXSPLTIB/VEXTSB2W) is not done. */
-
-vector int
-v4si_const_1 (void)
-{
- return (vector int) { 1, 1, 1, 1 }; /* VSLTPISW. */
-}
-
-vector int
-v4si_const_126 (void)
-{
- return (vector int) { 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_const_1023 (void)
-{
- return (vector int) { 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_splats_1 (void)
-{
- return vec_splats (1); /* VSLTPISW. */
-}
-
-vector int
-v4si_splats_126 (void)
-{
- return vec_splats (126); /* XXSPLTIW. */
-}
-
-vector int
-v8hi_splats_1023 (void)
-{
- return vec_splats (1023); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mvspltisw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvextsb2w\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
deleted file mode 100644
index 59418d3bb0a..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V8HI vector constants. We make sure
- the power9 support (XXSPLTIB/VUPKLSB) is not done. */
-
-vector short
-v8hi_const_1 (void)
-{
- return (vector short) { 1, 1, 1, 1, 1, 1, 1, 1 }; /* VSLTPISH. */
-}
-
-vector short
-v8hi_const_126 (void)
-{
- return (vector short) { 126, 126, 126, 126,
- 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_const_1023 (void)
-{
- return (vector short) { 1023, 1023, 1023, 1023,
- 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1 (void)
-{
- return vec_splats ((short)1); /* VSLTPISH. */
-}
-
-vector short
-v8hi_splats_126 (void)
-{
- return vec_splats ((short)126); /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1023 (void)
-{
- return vec_splats ((short)1023); /* XXSPLTIW. */
-}
-
-/* Test that we can optimiza V8HI where all of the even elements are the same
- and all of the odd elements are the same. */
-vector short
-v8hi_const_1023_1000 (void)
-{
- return (vector short) { 1023, 1000, 1023, 1000,
- 1023, 1000, 1023, 1000 }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mvspltish\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvupklsb\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
index 6ed60dfcb98..a135279b1d7 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
@@ -149,6 +149,8 @@ main (int argc, char *argv [])
return 0;
}
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mxxspltiw\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
+
+
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