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* [gcc(refs/users/meissner/heads/work067)] Revert patch.
@ 2021-09-08 21:51 Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2021-09-08 21:51 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:80897a4e3d5ea9a423217eec1b8446108626f888
commit 80897a4e3d5ea9a423217eec1b8446108626f888
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Sep 8 17:50:27 2021 -0400
Revert patch.
2021-09-08 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patch.
* config/rs6000/rs6000.c (rs6000_emit_move_si_sf_subreg): Deal
with SUBREGs of TImode and DImode.
* config/rs6000/rs6000.md (SI_DI_TI): New mode iterator.
(movsf_from_<mode>): Replace movsf_from_si to add support for
subregs of DImode and TImode.
Diff:
---
gcc/config/rs6000/rs6000.c | 13 -------------
gcc/config/rs6000/rs6000.md | 15 +++++----------
2 files changed, 5 insertions(+), 23 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index bd1ae1f8d6e..b9ebd56c993 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -10942,19 +10942,6 @@ rs6000_emit_move_si_sf_subreg (rtx dest, rtx source, machine_mode mode)
return true;
}
- /* Deal with subregs of SI/DI/TImode. */
- if (mode == SFmode && inner_mode == TImode)
- {
- emit_insn (gen_movsf_from_ti (dest, inner_source));
- return true;
- }
-
- if (mode == SFmode && inner_mode == DImode)
- {
- emit_insn (gen_movsf_from_di (dest, inner_source));
- return true;
- }
-
if (mode == SFmode && inner_mode == SImode)
{
emit_insn (gen_movsf_from_si (dest, inner_source));
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 88fec34c87f..d6af66a1728 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -472,9 +472,6 @@
; Integer modes supported in VSX registers with ISA 3.0 instructions
(define_mode_iterator INT_ISA3 [QI HI SI DI])
-; Any supported integer mode that is at least 32-bits in size.
-(define_mode_iterator SI_DI_TI [SI DI TI])
-
; Everything we can extend QImode to.
(define_mode_iterator EXTQI [SI (DI "TARGET_POWERPC64")])
@@ -7864,11 +7861,11 @@
;; LWZ LFS LXSSP LXSSPX STW STFIWX
;; STXSIWX GPR->VSX VSX->GPR GPR->GPR
-(define_insn_and_split "movsf_from_<mode>"
+(define_insn_and_split "movsf_from_si"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, Z,
Z, wa, ?r, !r")
- (unspec:SF [(match_operand:SI_DI_TI 1 "input_operand"
+ (unspec:SF [(match_operand:SI 1 "input_operand"
"m, m, wY, Z, r, f,
wa, r, wa, r")]
UNSPEC_SF_FROM_SI))
@@ -7877,7 +7874,7 @@
X, r, X, X"))]
"TARGET_NO_SF_SUBREG
&& (register_operand (operands[0], SFmode)
- || register_operand (operands[1], <MODE>mode))"
+ || register_operand (operands[1], SImode))"
"@
lwz%U1%X1 %0,%1
lfs%U1%X1 %0,%1
@@ -7892,15 +7889,13 @@
"&& reload_completed
&& vsx_reg_sfsubreg_ok (operands[0], SFmode)
- && int_reg_operand_not_pseudo (operands[1], <MODE>mode)"
+ && int_reg_operand_not_pseudo (operands[1], SImode)"
[(const_int 0)]
{
rtx op0 = operands[0];
rtx op1 = operands[1];
rtx op2 = operands[2];
- rtx op1_di = ((<MODE>mode == SImode)
- ? gen_rtx_REG (DImode, reg_or_subregno (op1))
- : gen_lowpart (DImode, op1));
+ rtx op1_di = gen_rtx_REG (DImode, REGNO (op1));
/* Move SF value to upper 32-bits for xscvspdpn. */
emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));
^ permalink raw reply [flat|nested] 4+ messages in thread
* [gcc(refs/users/meissner/heads/work067)] Revert patch.
@ 2021-09-08 17:57 Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2021-09-08 17:57 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:9620d186d5b3f29854ca443d4643359cf21ceeb9
commit 9620d186d5b3f29854ca443d4643359cf21ceeb9
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Sep 8 13:56:44 2021 -0400
Revert patch.
2021-09-08 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patch
* config/rs6000/rs6000.c (rs6000_emit_move_si_sf_subreg): Deal
with SUBREGs of TImode and DImode.
* config/rs6000/rs6000.md (SI_DI_TI): New mode iterator.
(movsf_from_<mode>): Replace movsf_from_si to add support for
subregs of DImode and TImode.
Diff:
---
gcc/config/rs6000/rs6000.c | 17 ++++++++++++-----
gcc/config/rs6000/rs6000.md | 15 ++++-----------
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index bd1ae1f8d6e..da5abe6f7b5 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -10942,16 +10942,23 @@ rs6000_emit_move_si_sf_subreg (rtx dest, rtx source, machine_mode mode)
return true;
}
- /* Deal with subregs of SI/DI/TImode. */
- if (mode == SFmode && inner_mode == TImode)
+ /* In case we are given a SUBREG for a larger type, reduce it to
+ SImode. */
+ if (mode == SFmode && GET_MODE_SIZE (inner_mode) > 4)
{
- emit_insn (gen_movsf_from_ti (dest, inner_source));
+ rtx tmp = gen_reg_rtx (SImode);
+ emit_move_insn (tmp, gen_lowpart (SImode, source));
+ emit_insn (gen_movsf_from_si (dest, tmp));
return true;
}
- if (mode == SFmode && inner_mode == DImode)
+ /* In case we are given a SUBREG for a larger type, reduce it to
+ SImode. */
+ if (mode == SFmode && GET_MODE_SIZE (inner_mode) > 4)
{
- emit_insn (gen_movsf_from_di (dest, inner_source));
+ rtx tmp = gen_reg_rtx (SImode);
+ emit_move_insn (tmp, gen_lowpart (SImode, source));
+ emit_insn (gen_movsf_from_si (dest, tmp));
return true;
}
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index bce19310321..d6af66a1728 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -466,9 +466,6 @@
; Any supported integer mode.
(define_mode_iterator INT [QI HI SI DI TI PTI])
-; Any supported integer mode that is at least 32-bits in size.
-(define_mode_iterator SI_DI_TI [SI DI TI])
-
; Any supported integer mode that fits in one register.
(define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
@@ -7864,11 +7861,11 @@
;; LWZ LFS LXSSP LXSSPX STW STFIWX
;; STXSIWX GPR->VSX VSX->GPR GPR->GPR
-(define_insn_and_split "movsf_from_<mode>"
+(define_insn_and_split "movsf_from_si"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, Z,
Z, wa, ?r, !r")
- (unspec:SF [(match_operand:SI_DI_TI 1 "input_operand"
+ (unspec:SF [(match_operand:SI 1 "input_operand"
"m, m, wY, Z, r, f,
wa, r, wa, r")]
UNSPEC_SF_FROM_SI))
@@ -7877,7 +7874,7 @@
X, r, X, X"))]
"TARGET_NO_SF_SUBREG
&& (register_operand (operands[0], SFmode)
- || register_operand (operands[1], <MODE>mode))"
+ || register_operand (operands[1], SImode))"
"@
lwz%U1%X1 %0,%1
lfs%U1%X1 %0,%1
@@ -7892,16 +7889,12 @@
"&& reload_completed
&& vsx_reg_sfsubreg_ok (operands[0], SFmode)
- && int_reg_operand_not_pseudo (operands[1], <MODE>mode)"
+ && int_reg_operand_not_pseudo (operands[1], SImode)"
[(const_int 0)]
{
rtx op0 = operands[0];
rtx op1 = operands[1];
rtx op2 = operands[2];
-
- if (GET_MODE (op1) != SImode)
- op1 = gen_lowpart (SImode, op1);
-
rtx op1_di = gen_rtx_REG (DImode, REGNO (op1));
/* Move SF value to upper 32-bits for xscvspdpn. */
^ permalink raw reply [flat|nested] 4+ messages in thread
* [gcc(refs/users/meissner/heads/work067)] Revert patch.
@ 2021-09-08 16:31 Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2021-09-08 16:31 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:ac87de6541cb686a9922a4f293f21ab3fff4100d
commit ac87de6541cb686a9922a4f293f21ab3fff4100d
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Sep 8 12:30:49 2021 -0400
Revert patch.
2021-09-08 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patch.
* config/rs6000/rs6000.c (rs6000_emit_move_si_sf_subreg): Deal
with SUBREGs of TImode and DImode.
Diff:
---
gcc/config/rs6000/rs6000.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 7bbf29a3e1c..da5abe6f7b5 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -10952,6 +10952,16 @@ rs6000_emit_move_si_sf_subreg (rtx dest, rtx source, machine_mode mode)
return true;
}
+ /* In case we are given a SUBREG for a larger type, reduce it to
+ SImode. */
+ if (mode == SFmode && GET_MODE_SIZE (inner_mode) > 4)
+ {
+ rtx tmp = gen_reg_rtx (SImode);
+ emit_move_insn (tmp, gen_lowpart (SImode, source));
+ emit_insn (gen_movsf_from_si (dest, tmp));
+ return true;
+ }
+
if (mode == SFmode && inner_mode == SImode)
{
emit_insn (gen_movsf_from_si (dest, inner_source));
^ permalink raw reply [flat|nested] 4+ messages in thread
* [gcc(refs/users/meissner/heads/work067)] Revert patch.
@ 2021-09-06 21:10 Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2021-09-06 21:10 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:6ee5caa3fc0e1ad9f5fab62926a564c7ebf9272e
commit 6ee5caa3fc0e1ad9f5fab62926a564c7ebf9272e
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Sep 6 17:10:21 2021 -0400
Revert patch.
2021-09-06 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patch.
* config/rs6000/rs6000.c (rs6000_emit_move_si_sf_subreg): Deal
with SUBREGs of TImode and DImode.
Diff:
---
gcc/config/rs6000/rs6000.c | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 5c681c1f15c..b9ebd56c993 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -10942,16 +10942,6 @@ rs6000_emit_move_si_sf_subreg (rtx dest, rtx source, machine_mode mode)
return true;
}
- if (mode == SFmode && GET_MODE_SIZE (inner_mode) > 4)
- {
- rtx tmp = gen_reg_rtx (SImode);
-
- debug_rtx (source);
- emit_move_insn (tmp, gen_lowpart (SImode, source));
- emit_insn (gen_movsf_from_si (dest, tmp));
- return true;
- }
-
if (mode == SFmode && inner_mode == SImode)
{
emit_insn (gen_movsf_from_si (dest, inner_source));
^ permalink raw reply [flat|nested] 4+ messages in thread
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